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GET /api/patches/105121/?format=api
{ "id": 105121, "url": "http://patches.dpdk.org/api/patches/105121/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211213211425.6332-4-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211213211425.6332-4-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211213211425.6332-4-pbhagavatula@marvell.com", "date": "2021-12-13T21:14:24", "name": "[4/4] net/cnxk: improve Rx performance", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f05e64667305c2736804c182e6d3f7410c7a3fb5", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211213211425.6332-4-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 20936, "url": "http://patches.dpdk.org/api/series/20936/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20936", "date": "2021-12-13T21:14:21", "name": "[1/4] net/cnxk: avoid command copy from Tx queue", "version": 1, "mbox": "http://patches.dpdk.org/series/20936/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105121/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/105121/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E70A5A034D;\n\tMon, 13 Dec 2021 22:15:45 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0FF9B41145;\n\tMon, 13 Dec 2021 22:15:36 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 55DFC406FF\n for <dev@dpdk.org>; Mon, 13 Dec 2021 22:15:34 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1BDElBZE029954\n for <dev@dpdk.org>; Mon, 13 Dec 2021 13:15:33 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cx88ahnnb-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 13 Dec 2021 13:15:33 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 13 Dec 2021 13:15:32 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 13 Dec 2021 13:15:32 -0800", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 711613F7079;\n Mon, 13 Dec 2021 13:15:29 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=KaKwfhxut6Yb5B9aWOttwwKLW4/M5L6qWTIes774Mh4=;\n b=e3O7NXeDFs6XKRsbOtmyqVkcxd6WVCQvCBTl2w0O6gHHNgBgoI0KpFBLjCvdePdd9iMQ\n UXiCYFD9D6yltpsQ6PrLS+uCFvK2V5LPbqOQzOBdBHSHy9/0qtgaFa0kwJKL5cmfYP/+\n Ow+IZ2ax8ERgd+OXkFphwLv7fMQSOtAfp6mXwm8Yl/De46PpXoNqwea3bhE1bOjntQRm\n uZETAGbgpArLUYYGYC60DqCWZinlkTrwsE6TsG1avqBzXLjHWyx+lKhCWBSVtfJKsP6R\n fYl0DOy0IW78c9wuG1QfSRKO0q0qERGioDtJtiMUyIaK3eltrA49RmzE9bxsbP/PWDLQ zg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>,\n Kiran Kumar K <kirankumark@marvell.com>, Sunil Kumar Kori\n <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 4/4] net/cnxk: improve Rx performance", "Date": "Tue, 14 Dec 2021 02:44:24 +0530", "Message-ID": "<20211213211425.6332-4-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211213211425.6332-1-pbhagavatula@marvell.com>", "References": "<20211213211425.6332-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "Eebs81Wx_tLSNB9ypSHy9Vp_-mzhD2J2", "X-Proofpoint-ORIG-GUID": "Eebs81Wx_tLSNB9ypSHy9Vp_-mzhD2J2", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-13_10,2021-12-13_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nImprove vWQE and CQ Rx performance by tuning perfetches to 64B\ncacheline size.\nAlso, prefetch the vWQE array offsets at cacheline boundaries.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/cnxk/cn10k_worker.h | 25 +++++++++++++++----------\n drivers/net/cnxk/cn10k_rx.h | 8 ++++----\n drivers/net/cnxk/cn9k_rx.h | 20 ++++++++++----------\n 3 files changed, 29 insertions(+), 24 deletions(-)\n\n--\n2.17.1", "diff": "diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex 65602a632e..6e77d32827 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -118,11 +118,17 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,\n \tuint8_t loff = 0;\n \tuint64_t sa_base;\n \tuint64_t **wqe;\n+\tint i;\n\n \tmbuf_init |= ((uint64_t)port_id) << 48;\n \tvec = (struct rte_event_vector *)vwqe;\n \twqe = vec->u64s;\n\n+\trte_prefetch_non_temporal(&vec->ptrs[0]);\n+#define OBJS_PER_CLINE (RTE_CACHE_LINE_SIZE / sizeof(void *))\n+\tfor (i = OBJS_PER_CLINE; i < vec->nb_elem; i += OBJS_PER_CLINE)\n+\t\trte_prefetch_non_temporal(&vec->ptrs[i]);\n+\n \tnb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP);\n \tnb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, vec->mbufs, nb_mbufs,\n \t\t\t\t\t flags | NIX_RX_VWQE_F, lookup_mem,\n@@ -191,15 +197,13 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \t\tuint64_t u64[2];\n \t} gw;\n \tuint64_t tstamp_ptr;\n-\tuint64_t mbuf;\n\n \tgw.get_work = ws->gw_wdata;\n #if defined(RTE_ARCH_ARM64) && !defined(__clang__)\n \tasm volatile(\n \t\tPLT_CPU_FEATURE_PREAMBLE\n-\t\t\"caspl %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\\n\"\n-\t\t\"sub %[mbuf], %H[wdata], #0x80\t\t\t\t\\n\"\n-\t\t: [wdata] \"+r\"(gw.get_work), [mbuf] \"=&r\"(mbuf)\n+\t\t\"caspal %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\\n\"\n+\t\t: [wdata] \"+r\"(gw.get_work)\n \t\t: [gw_loc] \"r\"(ws->base + SSOW_LF_GWS_OP_GET_WORK0)\n \t\t: \"memory\");\n #else\n@@ -208,14 +212,12 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \t\troc_load_pair(gw.u64[0], gw.u64[1],\n \t\t\t ws->base + SSOW_LF_GWS_WQE0);\n \t} while (gw.u64[0] & BIT_ULL(63));\n-\tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n \tws->gw_rdata = gw.u64[0];\n-\tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n-\t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n-\t\t (gw.u64[0] & 0xffffffff);\n-\n-\tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n+\tif (gw.u64[1]) {\n+\t\tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n+\t\t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n+\t\t\t (gw.u64[0] & 0xffffffff);\n \t\tif ((flags & CPT_RX_WQE_F) &&\n \t\t (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n \t\t RTE_EVENT_TYPE_CRYPTODEV)) {\n@@ -223,7 +225,10 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \t\t} else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n \t\t\t RTE_EVENT_TYPE_ETHDEV) {\n \t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n+\t\t\tuint64_t mbuf;\n\n+\t\t\tmbuf = gw.u64[1] - sizeof(struct rte_mbuf);\n+\t\t\trte_prefetch0((void *)mbuf);\n \t\t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n \t\t\t\tstruct rte_mbuf *m;\n \t\t\t\tuintptr_t sa_base;\ndiff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nindex a2442d3726..9694a3080f 100644\n--- a/drivers/net/cnxk/cn10k_rx.h\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -610,10 +610,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t}\n\n \t\t/* Prefetch N desc ahead */\n-\t\trte_prefetch_non_temporal(CQE_PTR_OFF(cq0, 8, 0, flags));\n-\t\trte_prefetch_non_temporal(CQE_PTR_OFF(cq0, 9, 0, flags));\n-\t\trte_prefetch_non_temporal(CQE_PTR_OFF(cq0, 10, 0, flags));\n-\t\trte_prefetch_non_temporal(CQE_PTR_OFF(cq0, 11, 0, flags));\n+\t\trte_prefetch_non_temporal(CQE_PTR_OFF(cq0, 4, 64, flags));\n+\t\trte_prefetch_non_temporal(CQE_PTR_OFF(cq0, 5, 64, flags));\n+\t\trte_prefetch_non_temporal(CQE_PTR_OFF(cq0, 6, 64, flags));\n+\t\trte_prefetch_non_temporal(CQE_PTR_OFF(cq0, 7, 64, flags));\n\n \t\t/* Get NIX_RX_SG_S for size and buffer pointer */\n \t\tcq0_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 0, 64, flags));\ndiff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h\nindex b038b1a6ef..fa4efbf80a 100644\n--- a/drivers/net/cnxk/cn9k_rx.h\n+++ b/drivers/net/cnxk/cn9k_rx.h\n@@ -342,16 +342,16 @@ cn9k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n \t\tol_flags =\n \t\t\tnix_update_match_id(rx->cn9k.match_id, ol_flags, mbuf);\n\n-\tmbuf->pkt_len = len;\n-\tmbuf->data_len = len;\n-\t*(uint64_t *)(&mbuf->rearm_data) = val;\n-\n \tmbuf->ol_flags = ol_flags;\n+\t*(uint64_t *)(&mbuf->rearm_data) = val;\n+\tmbuf->pkt_len = len;\n\n-\tif (flag & NIX_RX_MULTI_SEG_F)\n+\tif (flag & NIX_RX_MULTI_SEG_F) {\n \t\tnix_cqe_xtract_mseg(rx, mbuf, val, flag);\n-\telse\n+\t} else {\n+\t\tmbuf->data_len = len;\n \t\tmbuf->next = NULL;\n+\t}\n }\n\n static inline uint16_t\n@@ -723,10 +723,6 @@ cn9k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tvst1q_u64((uint64_t *)mbuf2->rearm_data, rearm2);\n \t\tvst1q_u64((uint64_t *)mbuf3->rearm_data, rearm3);\n\n-\t\t/* Store the mbufs to rx_pkts */\n-\t\tvst1q_u64((uint64_t *)&rx_pkts[packets], mbuf01);\n-\t\tvst1q_u64((uint64_t *)&rx_pkts[packets + 2], mbuf23);\n-\n \t\tif (flags & NIX_RX_MULTI_SEG_F) {\n \t\t\t/* Multi segment is enable build mseg list for\n \t\t\t * individual mbufs in scalar mode.\n@@ -751,6 +747,10 @@ cn9k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\tmbuf3->next = NULL;\n \t\t}\n\n+\t\t/* Store the mbufs to rx_pkts */\n+\t\tvst1q_u64((uint64_t *)&rx_pkts[packets], mbuf01);\n+\t\tvst1q_u64((uint64_t *)&rx_pkts[packets + 2], mbuf23);\n+\n \t\t/* Prefetch mbufs */\n \t\troc_prefetch_store_keep(mbuf0);\n \t\troc_prefetch_store_keep(mbuf1);\n", "prefixes": [ "4/4" ] }