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GET /api/patches/105119/?format=api
{ "id": 105119, "url": "http://patches.dpdk.org/api/patches/105119/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211213211425.6332-2-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211213211425.6332-2-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211213211425.6332-2-pbhagavatula@marvell.com", "date": "2021-12-13T21:14:22", "name": "[2/4] event/cnxk: store and reuse workslot status", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "82cc2273fa8ed6d7489a25cd7339730fccd37061", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211213211425.6332-2-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 20936, "url": "http://patches.dpdk.org/api/series/20936/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20936", "date": "2021-12-13T21:14:21", "name": "[1/4] net/cnxk: avoid command copy from Tx queue", "version": 1, "mbox": "http://patches.dpdk.org/series/20936/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105119/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/105119/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 398C9A034D;\n\tMon, 13 Dec 2021 22:15:35 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3C58741144;\n\tMon, 13 Dec 2021 22:15:30 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 9163E410FD\n for <dev@dpdk.org>; Mon, 13 Dec 2021 22:15:27 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1BDElFcF030003\n for <dev@dpdk.org>; Mon, 13 Dec 2021 13:15:26 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cx88ahnmc-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 13 Dec 2021 13:15:26 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 13 Dec 2021 13:15:25 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 13 Dec 2021 13:15:25 -0800", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 4859B3F704A;\n Mon, 13 Dec 2021 13:15:22 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=0tbKQY3YnFpiYokYygYzVG5IbfhXbHrmFt3guMChWEE=;\n b=aX17xC6O1O/MqK003n5d6q37EA9ybiHn/XTKY3+G0EZHleM+EdaHAvRorZyQH2xtTrGo\n Wb69jhmyR6cEa5EALgR5NxSsWqkrUQSI9pQ6bYqK8LrwAUNmQMFpQ7ei6F2SmLKOjIlq\n WKTpoEaxAXy5CFo6DDFqEATpKvVSf47MnnEbBvfJH8DlOBFbkog/HeoFFF1dLvpq0vLP\n ra3NHT1yKPI5aiel1X3eAf2rxwjJN9+EYfCps/35MllVGqd3ea4v55FC9owoyH2mE8uZ\n 3NS28WNQHOafkzUm2LmxfesnVyikx2eo5LcPgG3AQefZowz8LcVjUd0iWlgODuyNm5ba LQ==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Pavan Nikhilesh\n <pbhagavatula@marvell.com>, Shijith Thotton <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 2/4] event/cnxk: store and reuse workslot status", "Date": "Tue, 14 Dec 2021 02:44:22 +0530", "Message-ID": "<20211213211425.6332-2-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211213211425.6332-1-pbhagavatula@marvell.com>", "References": "<20211213211425.6332-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "lFcT46mnYw99gwEZ1wwjHuPKvvxlAYtM", "X-Proofpoint-ORIG-GUID": "lFcT46mnYw99gwEZ1wwjHuPKvvxlAYtM", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-13_10,2021-12-13_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nStore and reuse workslot status for TT, GRP and HEAD status\ninstead of reading from GWC as reading from GWC imposes\nadditional latency.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/common/cnxk/roc_sso.h | 11 ++++++-----\n drivers/event/cnxk/cn10k_worker.h | 17 ++++++++++-------\n drivers/event/cnxk/cnxk_eventdev.h | 2 ++\n drivers/event/cnxk/cnxk_worker.h | 11 +++++++----\n drivers/net/cnxk/cn10k_tx.h | 12 ++++++------\n 5 files changed, 31 insertions(+), 22 deletions(-)\n\n--\n2.17.1", "diff": "diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h\nindex 27d49c6c68..9c594f5c1c 100644\n--- a/drivers/common/cnxk/roc_sso.h\n+++ b/drivers/common/cnxk/roc_sso.h\n@@ -54,12 +54,12 @@ struct roc_sso {\n \tuint8_t reserved[ROC_SSO_MEM_SZ] __plt_cache_aligned;\n } __plt_cache_aligned;\n\n-static __plt_always_inline void\n+static __plt_always_inline uint64_t\n roc_sso_hws_head_wait(uintptr_t tag_op)\n {\n-#ifdef RTE_ARCH_ARM64\n \tuint64_t tag;\n\n+#ifdef RTE_ARCH_ARM64\n \tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n \t\t \"\t\tldr %[tag], [%[tag_op]]\t\\n\"\n \t\t \"\t\ttbnz %[tag], 35, done%=\t\t\\n\"\n@@ -71,10 +71,11 @@ roc_sso_hws_head_wait(uintptr_t tag_op)\n \t\t : [tag] \"=&r\"(tag)\n \t\t : [tag_op] \"r\"(tag_op));\n #else\n-\t/* Wait for the SWTAG/SWTAG_FULL operation */\n-\twhile (!(plt_read64(tag_op) & BIT_ULL(35)))\n-\t\t;\n+\tdo {\n+\t\ttag = plt_read64(tag_op);\n+\t} while (!(tag & BIT_ULL(35)));\n #endif\n+\treturn tag;\n }\n\n /* SSO device initialization */\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex e80e4fb895..65602a632e 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -40,8 +40,7 @@ cn10k_sso_hws_fwd_swtag(struct cn10k_sso_hws *ws, const struct rte_event *ev)\n {\n \tconst uint32_t tag = (uint32_t)ev->event;\n \tconst uint8_t new_tt = ev->sched_type;\n-\tconst uint8_t cur_tt =\n-\t\tCNXK_TT_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_WQE0));\n+\tconst uint8_t cur_tt = CNXK_TT_FROM_TAG(ws->gw_rdata);\n\n \t/* CNXK model\n \t * cur_tt/new_tt SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED\n@@ -81,7 +80,7 @@ cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,\n \tconst uint8_t grp = ev->queue_id;\n\n \t/* Group hasn't changed, Use SWTAG to forward the event */\n-\tif (CNXK_GRP_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_WQE0)) == grp)\n+\tif (CNXK_GRP_FROM_TAG(ws->gw_rdata) == grp)\n \t\tcn10k_sso_hws_fwd_swtag(ws, ev);\n \telse\n \t\t/*\n@@ -211,6 +210,7 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \t} while (gw.u64[0] & BIT_ULL(63));\n \tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n+\tws->gw_rdata = gw.u64[0];\n \tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n \t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n \t\t (gw.u64[0] & 0xffffffff);\n@@ -406,7 +406,8 @@ NIX_RX_FASTPATH_MODES\n \t\tRTE_SET_USED(timeout_ticks); \\\n \t\tif (ws->swtag_req) { \\\n \t\t\tws->swtag_req = 0; \\\n-\t\t\tcnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0); \\\n+\t\t\tws->gw_rdata = cnxk_sso_hws_swtag_wait( \\\n+\t\t\t\tws->base + SSOW_LF_GWS_WQE0); \\\n \t\t\treturn 1; \\\n \t\t} \\\n \t\treturn cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n@@ -426,7 +427,8 @@ NIX_RX_FASTPATH_MODES\n \\\n \t\tif (ws->swtag_req) { \\\n \t\t\tws->swtag_req = 0; \\\n-\t\t\tcnxk_sso_hws_swtag_wait(ws->base + SSOW_LF_GWS_WQE0); \\\n+\t\t\tws->gw_rdata = cnxk_sso_hws_swtag_wait( \\\n+\t\t\t\tws->base + SSOW_LF_GWS_WQE0); \\\n \t\t\treturn ret; \\\n \t\t} \\\n \t\tret = cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n@@ -509,8 +511,9 @@ cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd,\n \telse\n \t\tpa = txq->io_addr | ((segdw - 1) << 4);\n\n-\tif (!sched_type)\n-\t\troc_sso_hws_head_wait(ws->base + SSOW_LF_GWS_TAG);\n+\tif (!CNXK_TAG_IS_HEAD(ws->gw_rdata) && !sched_type)\n+\t\tws->gw_rdata =\n+\t\t\troc_sso_hws_head_wait(ws->base + SSOW_LF_GWS_TAG);\n\n \troc_lmt_submit_steorl(lmt_id, pa);\n }\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex b26df58588..ab58508590 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -47,6 +47,7 @@\n #define CNXK_CLR_SUB_EVENT(x)\t (~(0xffu << 20) & x)\n #define CNXK_GRP_FROM_TAG(x)\t (((x) >> 36) & 0x3ff)\n #define CNXK_SWTAG_PEND(x)\t (BIT_ULL(62) & x)\n+#define CNXK_TAG_IS_HEAD(x)\t (BIT_ULL(35) & x)\n\n #define CN9K_SSOW_GET_BASE_ADDR(_GW) ((_GW)-SSOW_LF_GWS_OP_GET_WORK0)\n\n@@ -123,6 +124,7 @@ struct cnxk_sso_evdev {\n\n struct cn10k_sso_hws {\n \tuint64_t base;\n+\tuint64_t gw_rdata;\n \t/* PTP timestamp */\n \tstruct cnxk_timesync_info *tstamp;\n \tvoid *lookup_mem;\ndiff --git a/drivers/event/cnxk/cnxk_worker.h b/drivers/event/cnxk/cnxk_worker.h\nindex 9f9ceab8a1..7de03f3fbb 100644\n--- a/drivers/event/cnxk/cnxk_worker.h\n+++ b/drivers/event/cnxk/cnxk_worker.h\n@@ -52,11 +52,11 @@ cnxk_sso_hws_swtag_flush(uint64_t tag_op, uint64_t flush_op)\n \tplt_write64(0, flush_op);\n }\n\n-static __rte_always_inline void\n+static __rte_always_inline uint64_t\n cnxk_sso_hws_swtag_wait(uintptr_t tag_op)\n {\n-#ifdef RTE_ARCH_ARM64\n \tuint64_t swtp;\n+#ifdef RTE_ARCH_ARM64\n\n \tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n \t\t \"\t\tldr %[swtb], [%[swtp_loc]]\t\\n\"\n@@ -70,9 +70,12 @@ cnxk_sso_hws_swtag_wait(uintptr_t tag_op)\n \t\t : [swtp_loc] \"r\"(tag_op));\n #else\n \t/* Wait for the SWTAG/SWTAG_FULL operation */\n-\twhile (plt_read64(tag_op) & BIT_ULL(62))\n-\t\t;\n+\tdo {\n+\t\tswtp = plt_read64(tag_op);\n+\t} while (swtp & BIT_ULL(62));\n #endif\n+\n+\treturn swtp;\n }\n\n #endif\ndiff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h\nindex b3034c72cb..8b2f1c868e 100644\n--- a/drivers/net/cnxk/cn10k_tx.h\n+++ b/drivers/net/cnxk/cn10k_tx.h\n@@ -905,8 +905,8 @@ cn10k_nix_xmit_pkts(void *tx_queue, uint64_t *ws, struct rte_mbuf **tx_pkts,\n \t\t\tlnum++;\n \t}\n\n-\tif (flags & NIX_TX_VWQE_F)\n-\t\troc_sso_hws_head_wait(ws[0]);\n+\tif ((flags & NIX_TX_VWQE_F) && !(ws[1] & BIT_ULL(35)))\n+\t\tws[1] = roc_sso_hws_head_wait(ws[0]);\n\n \tleft -= burst;\n \ttx_pkts += burst;\n@@ -1041,8 +1041,8 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, uint64_t *ws,\n \t\t}\n \t}\n\n-\tif (flags & NIX_TX_VWQE_F)\n-\t\troc_sso_hws_head_wait(ws[0]);\n+\tif ((flags & NIX_TX_VWQE_F) && !(ws[1] & BIT_ULL(35)))\n+\t\tws[1] = roc_sso_hws_head_wait(ws[0]);\n\n \tleft -= burst;\n \ttx_pkts += burst;\n@@ -2582,8 +2582,8 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,\n \tif (flags & (NIX_TX_MULTI_SEG_F | NIX_TX_OFFLOAD_SECURITY_F))\n \t\twd.data[0] >>= 16;\n\n-\tif (flags & NIX_TX_VWQE_F)\n-\t\troc_sso_hws_head_wait(ws[0]);\n+\tif ((flags & NIX_TX_VWQE_F) && !(ws[1] & BIT_ULL(35)))\n+\t\tws[1] = roc_sso_hws_head_wait(ws[0]);\n\n \tleft -= burst;\n\n", "prefixes": [ "2/4" ] }