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GET /api/patches/105116/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 105116,
    "url": "http://patches.dpdk.org/api/patches/105116/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211213205424.5588-1-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211213205424.5588-1-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211213205424.5588-1-pbhagavatula@marvell.com",
    "date": "2021-12-13T20:54:23",
    "name": "common/cnxk: add workaround for vWQE flush",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "74b776a903b9dbfa47074b242ec52826865c24c6",
    "submitter": {
        "id": 1183,
        "url": "http://patches.dpdk.org/api/people/1183/?format=api",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211213205424.5588-1-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 20934,
            "url": "http://patches.dpdk.org/api/series/20934/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20934",
            "date": "2021-12-13T20:54:23",
            "name": "common/cnxk: add workaround for vWQE flush",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/20934/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/105116/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/105116/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
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            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 76D81406A2;\n\tMon, 13 Dec 2021 21:54:33 +0100 (CET)",
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            "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cx88ahjw9-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 13 Dec 2021 12:54:30 -0800",
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        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=7jWCKZb4ivwx8ewTvgepVsOo32+fnF1M2LxcCGbs/0A=;\n b=Qi2SwWLNojTZZKYNQkm9xfm7KYWILA/OttzQBlarg1EFPkLD8wzvu4o8Z7PRt1hM7UId\n vwi//M3dz41izLcP0ILKjN2fUAt6y1SUUmQo+kNwTohHaHtpecrPeQ2NGiOexspAMIKs\n FSzcGxEqIOxNIehNvJDs7y1kfLhG+Qc1XdvyHgG12RVbPiw3H5pYJMePnmrWOHxBhVnl\n EKzamppquCNkRE2oRX8IjjtHErXgYlxMSBUidg+iouF6d325qDIxRbBpcP974oLJGXrM\n EYOZjD/memH32MQfJ1ARC6+LlOD4UEZu8WB+Q8UPKBN0TgLslO7pfYurVvY4HRcV/Kw/ 3w==",
        "From": "<pbhagavatula@marvell.com>",
        "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>",
        "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>",
        "Subject": "[PATCH] common/cnxk: add workaround for vWQE flush",
        "Date": "Tue, 14 Dec 2021 02:24:23 +0530",
        "Message-ID": "<20211213205424.5588-1-pbhagavatula@marvell.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-GUID": "f5hKsq0vUHR7kKOlSr_teyt3_jVip11B",
        "X-Proofpoint-ORIG-GUID": "f5hKsq0vUHR7kKOlSr_teyt3_jVip11B",
        "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-13_10,2021-12-13_01,2021-12-02_01",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
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        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nDue to an errata writing to vWQE flush register might hang NIX.\nAdd workaround for vWQE flush hang by waiting for the max\ncoalescing timeout to flush out any pending vWQEs.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/common/cnxk/roc_nix_inl.c      |  3 +--\n drivers/common/cnxk/roc_nix_inl_dev.c  | 12 ++++++++++++\n drivers/common/cnxk/roc_nix_inl_priv.h |  1 +\n drivers/common/cnxk/roc_nix_priv.h     |  1 +\n drivers/common/cnxk/roc_nix_queue.c    | 19 +++++++++++++++++--\n 5 files changed, 32 insertions(+), 4 deletions(-)",
    "diff": "diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex f0fc690417..e8981c4aa4 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -595,8 +595,7 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)\n \t\tplt_err(\"Failed to disable inline device rq, rc=%d\", rc);\n \n \t/* Flush NIX LF for CN10K */\n-\tif (roc_model_is_cn10k())\n-\t\tplt_write64(0, inl_dev->nix_base + NIX_LF_OP_VWQE_FLUSH);\n+\tnix_rq_vwqe_flush(rq, inl_dev->vwqe_interval);\n \n \treturn rc;\n }\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nindex a0fe6ecd82..10912a6c93 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -346,6 +346,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n \tstruct mbox *mbox = dev->mbox;\n \tstruct nix_lf_alloc_rsp *rsp;\n \tstruct nix_lf_alloc_req *req;\n+\tstruct nix_hw_info *hw_info;\n \tsize_t inb_sa_sz;\n \tint i, rc = -ENOSPC;\n \tvoid *sa;\n@@ -382,6 +383,17 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n \tinl_dev->qints = rsp->qints;\n \tinl_dev->cints = rsp->cints;\n \n+\t/* Get VWQE info if supported */\n+\tif (roc_model_is_cn10k()) {\n+\t\tmbox_alloc_msg_nix_get_hw_info(mbox);\n+\t\trc = mbox_process_msg(mbox, (void *)&hw_info);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to get HW info, rc=%d\", rc);\n+\t\t\tgoto lf_free;\n+\t\t}\n+\t\tinl_dev->vwqe_interval = hw_info->vwqe_delay;\n+\t}\n+\n \t/* Register nix interrupts */\n \trc = nix_inl_nix_register_irqs(inl_dev);\n \tif (rc) {\ndiff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h\nindex 3dc526f929..be53a3fa81 100644\n--- a/drivers/common/cnxk/roc_nix_inl_priv.h\n+++ b/drivers/common/cnxk/roc_nix_inl_priv.h\n@@ -35,6 +35,7 @@ struct nix_inl_dev {\n \t/* NIX data */\n \tuint8_t lf_tx_stats;\n \tuint8_t lf_rx_stats;\n+\tuint16_t vwqe_interval;\n \tuint16_t cints;\n \tuint16_t qints;\n \tstruct roc_nix_rq rq;\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 04575af295..deb2a6ba11 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -377,6 +377,7 @@ int nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n int nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable);\n int nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled);\n int nix_tm_bp_config_set(struct roc_nix *roc_nix, bool enable);\n+void nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval);\n \n /*\n  * TM priv utils.\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex c8c8401d81..d5f6813e69 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -28,6 +28,22 @@ nix_qsize_clampup(uint32_t val)\n \treturn i;\n }\n \n+void\n+nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval)\n+{\n+\tuint64_t wait_ns;\n+\n+\tif (!roc_model_is_cn10k())\n+\t\treturn;\n+\t/* Due to HW errata writes to VWQE_FLUSH might hang, so instead\n+\t * wait for max vwqe timeout interval.\n+\t */\n+\tif (rq->vwqe_ena) {\n+\t\twait_ns = rq->vwqe_wait_tmo * (vwqe_interval + 1) * 100;\n+\t\tplt_delay_us((wait_ns / 1E3) + 1);\n+\t}\n+}\n+\n int\n nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable)\n {\n@@ -66,9 +82,8 @@ roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable)\n \tint rc;\n \n \trc = nix_rq_ena_dis(&nix->dev, rq, enable);\n+\tnix_rq_vwqe_flush(rq, nix->vwqe_interval);\n \n-\tif (roc_model_is_cn10k())\n-\t\tplt_write64(rq->qid, nix->base + NIX_LF_OP_VWQE_FLUSH);\n \treturn rc;\n }\n \n",
    "prefixes": []
}