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GET /api/patches/105071/?format=api
{ "id": 105071, "url": "http://patches.dpdk.org/api/patches/105071/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211211090435.2889574-2-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211211090435.2889574-2-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211211090435.2889574-2-jerinj@marvell.com", "date": "2021-12-11T09:04:31", "name": "[v5,1/5] common/cnxk: add REE HW definitions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "596c24f1b65a229e8c8eaca582721a62154437f7", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211211090435.2889574-2-jerinj@marvell.com/mbox/", "series": [ { "id": 20915, "url": "http://patches.dpdk.org/api/series/20915/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20915", "date": "2021-12-11T09:04:30", "name": "remove octeontx2 drivers", "version": 5, "mbox": "http://patches.dpdk.org/series/20915/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105071/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/105071/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1CB78A00C5;\n\tSat, 11 Dec 2021 10:08:51 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 94BA741142;\n\tSat, 11 Dec 2021 10:08:46 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 495124113F\n for <dev@dpdk.org>; Sat, 11 Dec 2021 10:08:45 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1BB7P7bK006238;\n Sat, 11 Dec 2021 01:08:44 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3cuv5hp4kv-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Sat, 11 Dec 2021 01:08:44 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 11 Dec 2021 01:08:42 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 11 Dec 2021 01:08:42 -0800", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n by maili.marvell.com (Postfix) with ESMTP id 6E6B13F7068;\n Sat, 11 Dec 2021 01:08:39 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=m+QhW18UH7U6oAMG0Dc46VfScTu4eti12bIQ6KArML8=;\n b=hrZwa8cj604xhprsdo3vNM/erLbI1v/PQh5+t5T4ZYjOMaN1kp6PF4bhL3yDEszwf6zL\n b4sVJJWDsfkX0JC5q0K80cZrIa/2Xt2FfWAlepcR7uwTNtle3gG3uljwTIU3YoXfEHBi\n xSfqr9ApPLiTNAGSYgtFztqn3uNUMR24Hzwn0y3Z0mXYNsAdLZS/MbdaQ7e9fSr34KdH\n AOcE/IrsaHMFb2qBzjKqLOufmnwM5DWE68+F3q9LEBZ1jUz4IEJ77k/+qWIkvSxY5zJq\n 3IaD6n0j0dL5r5gADwP78uVwK5a9RciffmWU7lD3E/htkhILbNRu18zOffdMVe2TyhB6 tA==", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>,\n <ferruh.yigit@intel.com>, Liron Himi <lironh@marvell.com>, Jerin Jacob\n <jerinj@marvell.com>", "Subject": "[dpdk-dev] [PATCH v5 1/5] common/cnxk: add REE HW definitions", "Date": "Sat, 11 Dec 2021 14:34:31 +0530", "Message-ID": "<20211211090435.2889574-2-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20211211090435.2889574-1-jerinj@marvell.com>", "References": "<20211207183143.27145-1-lironh@marvell.com>\n <20211211090435.2889574-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "LlAj2KY64KR-nUl2n9-7T0-BID7uvBm4", "X-Proofpoint-ORIG-GUID": "LlAj2KY64KR-nUl2n9-7T0-BID7uvBm4", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-11_03,2021-12-10_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Liron Himi <lironh@marvell.com>\n\nadding REE (Regular Expression Engine) HW definitions\n\nSigned-off-by: Liron Himi <lironh@marvell.com>\nAcked-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/common/cnxk/hw/ree.h | 126 +++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/hw/rvu.h | 5 ++\n 2 files changed, 131 insertions(+)\n create mode 100644 drivers/common/cnxk/hw/ree.h", "diff": "diff --git a/drivers/common/cnxk/hw/ree.h b/drivers/common/cnxk/hw/ree.h\nnew file mode 100644\nindex 0000000000..30af61d704\n--- /dev/null\n+++ b/drivers/common/cnxk/hw/ree.h\n@@ -0,0 +1,126 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __REE_HW_H__\n+#define __REE_HW_H__\n+\n+/* REE instruction queue length */\n+#define REE_IQ_LEN (1 << 13)\n+\n+#define REE_DEFAULT_CMD_QLEN REE_IQ_LEN\n+\n+/* Status register bits */\n+#define REE_STATUS_PMI_EOJ_BIT\t BIT_ULL(14)\n+#define REE_STATUS_PMI_SOJ_BIT\t BIT_ULL(13)\n+#define REE_STATUS_MP_CNT_DET_BIT BIT_ULL(7)\n+#define REE_STATUS_MM_CNT_DET_BIT BIT_ULL(6)\n+#define REE_STATUS_ML_CNT_DET_BIT BIT_ULL(5)\n+#define REE_STATUS_MST_CNT_DET_BIT BIT_ULL(4)\n+#define REE_STATUS_MPT_CNT_DET_BIT BIT_ULL(3)\n+\n+/* Register offsets */\n+/* REE LF registers */\n+#define REE_LF_DONE_INT\t\t0x120ull\n+#define REE_LF_DONE_INT_W1S\t0x130ull\n+#define REE_LF_DONE_INT_ENA_W1S 0x138ull\n+#define REE_LF_DONE_INT_ENA_W1C 0x140ull\n+#define REE_LF_MISC_INT\t\t0x300ull\n+#define REE_LF_MISC_INT_W1S\t0x310ull\n+#define REE_LF_MISC_INT_ENA_W1S 0x320ull\n+#define REE_LF_MISC_INT_ENA_W1C 0x330ull\n+#define REE_LF_ENA\t\t0x10ull\n+#define REE_LF_SBUF_ADDR\t0x20ull\n+#define REE_LF_DONE\t\t0x100ull\n+#define REE_LF_DONE_ACK\t\t0x110ull\n+#define REE_LF_DONE_WAIT\t0x148ull\n+#define REE_LF_DOORBELL\t\t0x400ull\n+#define REE_LF_OUTSTAND_JOB\t0x410ull\n+\n+/* BAR 0 */\n+#define REE_AF_REEXM_MAX_MATCH (0x80c8ull)\n+#define REE_AF_QUE_SBUF_CTL(a) (0x1200ull | (uint64_t)(a) << 3)\n+#define REE_PRIV_LF_CFG(a) (0x41000ull | (uint64_t)(a) << 3)\n+\n+#define REE_AF_QUEX_GMCTL(a) (0x800 | (a) << 3)\n+\n+#define REE_AF_INT_VEC_RAS\t(0x0ull)\n+#define REE_AF_INT_VEC_RVU\t(0x1ull)\n+#define REE_AF_INT_VEC_QUE_DONE (0x2ull)\n+#define REE_AF_INT_VEC_AQ\t(0x3ull)\n+\n+\n+#define REE_LF_INT_VEC_QUE_DONE (0x0ull)\n+#define REE_LF_INT_VEC_MISC\t(0x1ull)\n+\n+#define REE_LF_SBUF_ADDR_OFF_MASK GENMASK_ULL(6, 0)\n+#define REE_LF_SBUF_ADDR_PTR_MASK GENMASK_ULL(52, 7)\n+\n+#define REE_LF_ENA_ENA_MASK BIT_ULL(0)\n+\n+#define REE_LF_BAR2(vf, q_id) \\\n+\t((vf)->dev->bar2 + (((vf)->block_address << 20) | ((q_id) << 12)))\n+\n+#define REE_QUEUE_HI_PRIO 0x1\n+\n+enum ree_desc_type_e {\n+\tREE_TYPE_JOB_DESC = 0x0,\n+\tREE_TYPE_RESULT_DESC = 0x1,\n+\tREE_TYPE_ENUM_LAST = 0x2\n+};\n+\n+union ree_res_status {\n+\tuint64_t u;\n+\tstruct {\n+\t\tuint64_t job_type : 3;\n+\t\tuint64_t mpt_cnt_det : 1;\n+\t\tuint64_t mst_cnt_det : 1;\n+\t\tuint64_t ml_cnt_det : 1;\n+\t\tuint64_t mm_cnt_det : 1;\n+\t\tuint64_t mp_cnt_det : 1;\n+\t\tuint64_t mode : 2;\n+\t\tuint64_t reserved_10_11 : 2;\n+\t\tuint64_t reserved_12_12 : 1;\n+\t\tuint64_t pmi_soj : 1;\n+\t\tuint64_t pmi_eoj : 1;\n+\t\tuint64_t reserved_15_15 : 1;\n+\t\tuint64_t reserved_16_63 : 48;\n+\t} s;\n+};\n+\n+union ree_res {\n+\tuint64_t u[8];\n+\tstruct ree_res_s_98 {\n+\t\tuint64_t done : 1;\n+\t\tuint64_t hwjid : 7;\n+\t\tuint64_t ree_res_job_id : 24;\n+\t\tuint64_t ree_res_status : 16;\n+\t\tuint64_t ree_res_dmcnt : 8;\n+\t\tuint64_t ree_res_mcnt : 8;\n+\t\tuint64_t ree_meta_ptcnt : 16;\n+\t\tuint64_t ree_meta_icnt : 16;\n+\t\tuint64_t ree_meta_lcnt : 16;\n+\t\tuint64_t ree_pmi_min_byte_ptr : 16;\n+\t\tuint64_t ree_err : 1;\n+\t\tuint64_t reserved_129_190 : 62;\n+\t\tuint64_t doneint : 1;\n+\t\tuint64_t reserved_192_255 : 64;\n+\t\tuint64_t reserved_256_319 : 64;\n+\t\tuint64_t reserved_320_383 : 64;\n+\t\tuint64_t reserved_384_447 : 64;\n+\t\tuint64_t reserved_448_511 : 64;\n+\t} s;\n+};\n+\n+union ree_match {\n+\tuint64_t u;\n+\tstruct {\n+\t\tuint64_t ree_rule_id : 32;\n+\t\tuint64_t start_ptr : 14;\n+\t\tuint64_t reserved_46_47 : 2;\n+\t\tuint64_t match_length : 15;\n+\t\tuint64_t reserved_63_6 : 1;\n+\t} s;\n+};\n+\n+#endif /* __REE_HW_H__ */\ndiff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h\nindex 632d9499ea..daf758f0b5 100644\n--- a/drivers/common/cnxk/hw/rvu.h\n+++ b/drivers/common/cnxk/hw/rvu.h\n@@ -130,6 +130,7 @@\n #define RVU_BLOCK_TYPE_RAD (0xdull)\n #define RVU_BLOCK_TYPE_DFA (0xeull)\n #define RVU_BLOCK_TYPE_HNA (0xfull)\n+#define RVU_BLOCK_TYPE_REE (0xeull)\n \n #define RVU_BLOCK_ADDR_RVUM (0x0ull)\n #define RVU_BLOCK_ADDR_LMT (0x1ull)\n@@ -147,6 +148,8 @@\n #define RVU_BLOCK_ADDR_NDC2 (0xeull)\n #define RVU_BLOCK_ADDR_R_END (0x1full)\n #define RVU_BLOCK_ADDR_R_START (0x14ull)\n+#define RVU_BLOCK_ADDR_REE0 (0x14ull)\n+#define RVU_BLOCK_ADDR_REE1 (0x15ull)\n \n #define RVU_VF_INT_VEC_MBOX (0x0ull)\n \n@@ -167,6 +170,7 @@\n #define NPA_AF_BAR2_SEL\t (0x9000000ull)\n #define CPT_AF_BAR2_SEL\t (0x9000000ull)\n #define RVU_AF_BAR2_SEL\t (0x9000000ull)\n+#define REE_AF_BAR2_SEL\t (0x9000000ull)\n \n #define AF_BAR2_ALIASX(a, b) \\\n \t(0x9100000ull | (uint64_t)(a) << 12 | (uint64_t)(b))\n@@ -177,6 +181,7 @@\n #define NPA_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(0, b)\n #define CPT_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b)\n #define RVU_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b)\n+#define REE_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b)\n \n /* Structures definitions */\n \n", "prefixes": [ "v5", "1/5" ] }