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GET /api/patches/103953/?format=api
{ "id": 103953, "url": "http://patches.dpdk.org/api/patches/103953/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211108090704.3585175-5-g.singh@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211108090704.3585175-5-g.singh@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211108090704.3585175-5-g.singh@nxp.com", "date": "2021-11-08T09:07:01", "name": "[v3,4/7] dma/dpaa: support basic operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c53b1e2dd8938950d3b580a16738ae2528afe870", "submitter": { "id": 1068, "url": "http://patches.dpdk.org/api/people/1068/?format=api", "name": "Gagandeep Singh", "email": "g.singh@nxp.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211108090704.3585175-5-g.singh@nxp.com/mbox/", "series": [ { "id": 20374, "url": "http://patches.dpdk.org/api/series/20374/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20374", "date": "2021-11-08T09:06:57", "name": "Introduce DPAA DMA driver", "version": 3, "mbox": "http://patches.dpdk.org/series/20374/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103953/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/103953/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C87A8A0C4B;\n\tMon, 8 Nov 2021 10:07:56 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AB48D41120;\n\tMon, 8 Nov 2021 10:07:40 +0100 (CET)", "from EUR03-VE1-obe.outbound.protection.outlook.com\n (mail-eopbgr50065.outbound.protection.outlook.com [40.107.5.65])\n by mails.dpdk.org (Postfix) with ESMTP id 130A04113A\n for <dev@dpdk.org>; Mon, 8 Nov 2021 10:07:36 +0100 (CET)", "from VI1PR04MB6960.eurprd04.prod.outlook.com (2603:10a6:803:12d::10)\n by VE1PR04MB6495.eurprd04.prod.outlook.com (2603:10a6:803:11d::10)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.13; Mon, 8 Nov\n 2021 09:07:35 +0000", "from VI1PR04MB6960.eurprd04.prod.outlook.com\n ([fe80::11d9:6f32:90e:80c1]) by VI1PR04MB6960.eurprd04.prod.outlook.com\n ([fe80::11d9:6f32:90e:80c1%7]) with mapi id 15.20.4669.016; Mon, 8 Nov 2021\n 09:07:35 +0000", "from lsv03457.swis.in-blr01.nxp.com (14.142.151.118) by\n SG2PR02CA0077.apcprd02.prod.outlook.com (2603:1096:4:90::17) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.4669.11 via Frontend Transport; Mon, 8 Nov 2021 09:07:33 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=nUprzpdZqPJaDBWQZRov/qvtxLBbGWRkpx8Gb+2kF+bHwS5WbU2a5VsL1aAd6AJVzPNSHOtN13V2QflBFxhKBhntroz7ewFdtMnEvC6IGd5B2zbp9ZMYUkM+JkyQPuvxy+XhfPvQiCLtHWyBw5+3pt7W0Vm6UPTFQFWln1sRGLcA4V1xf/PGz1ZypHmrcY8XswAj/+7sDPMPJlfiELPmaZH7ySroxo6HTF3l6Hp73KtgeXmQbylJ6TfSInnswJlVEPFsaMd5dM2noW848kczTij6W2n5kVtwZYQBo07qkv891GawQPzJ07OyVUpiO1oIv5UwSKsQXZz/Z44kmjQV/w==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=wsoLu2PL226AIUi7WWksGB/ct6gznHPGCEHOSa3hcyo=;\n b=hTurwLfazUM5aiiYfdIVtrzuNT1tqQj0SeLD2SbHKmEr9UjuU2v2PMobvKxjOnM46o6s6sfKYvLQBiaedGzuRKre1Zi9NBbo9kZQrsIf7zSMwizrIXcSPCp3Lql2tT4xqFMHwo8OvCle7DdUtYH20MWO6Ns8r/nVNVMYdshzdVfBSWevJZpKW5nv9SToJRkHu1rijTSU6gdBqNKpIIKp94IrfZ6pDbhqiN+jUYxoKl+6MRXuZOjY9SaYMoMUpHtNEj19RQfeQmKqdXIAaYKKPWo2CRhxRDkOIXlu6R/Nf8Gw8NgUONpNBCClDcCYq7x//cYZAyXdXpZYCOOd6/gpvw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass\n header.d=nxp.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=wsoLu2PL226AIUi7WWksGB/ct6gznHPGCEHOSa3hcyo=;\n b=qsv03sPaT/L+p8TYr/t1/s7JVFBqQaK3uZEbEurykkCct9zHxaNQCvfrFdvkQvtOk8xdKp91jpl9oR+bWCjmnDJNrGvCBecCSUY3Ndm/L69EQG2Bsz3o67hPnHr5yaYLlHwzr8W0H0XAB2izcDWjBAMU/1myEUJ8yPvvL3Lyb2E=", "Authentication-Results": "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nxp.com;", "From": "Gagandeep Singh <g.singh@nxp.com>", "To": "dev@dpdk.org", "Cc": "nipun.gupta@nxp.com, thomas@monjalon.net,\n Gagandeep Singh <g.singh@nxp.com>", "Date": "Mon, 8 Nov 2021 14:37:01 +0530", "Message-Id": "<20211108090704.3585175-5-g.singh@nxp.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211108090704.3585175-1-g.singh@nxp.com>", "References": "<20211101085143.2472241-2-g.singh@nxp.com>\n <20211108090704.3585175-1-g.singh@nxp.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SG2PR02CA0077.apcprd02.prod.outlook.com\n (2603:1096:4:90::17) To VI1PR04MB6960.eurprd04.prod.outlook.com\n (2603:10a6:803:12d::10)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "1af7620f-f4b5-4646-9bc3-08d9a2973420", "X-MS-TrafficTypeDiagnostic": "VE1PR04MB6495:", "X-Microsoft-Antispam-PRVS": "\n <VE1PR04MB6495D5017155FEECFB53631DE1919@VE1PR04MB6495.eurprd04.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2958;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n jvlWKm0rlnDR4j7kdkZRNsVYmvZhMxuGl5j42Qks03csKAKV5sP0fyRIFI2rgHAymervjr+OFQjBxqKcyJi4nWEF/f173Kbj8x0XqEuPXSEiJhoBLiE89M6KIN+0RFBXiiwCFiWFcuwpFOMjyXhIdyc7PqosoO2lJFqyISe+HDe3drwT+qpB9jo9jE07OUX1oIG+DRw4QIWkWUMny8X/ybmlTNZUR4U20TvaZdnRqq2HAVB2rtcFFrbHe2NT9MP3UK8aABqM4gqsGiwtCtP7bO5P92kzegHzue+novQieFZhx8k9C3hw/mA67TJhD+YXX4RWOu7Tx4k8Z5fkC6D+JIMFiH72+eRoch8B4jKhVPeV/fBrlVOPQQiRAHa9WRh0IZNuD+ksAHXIn7XJV7WNjldFZT2xkCZSgjqzA3Hks1hbPje1Wf4mVHIiMw3UBGKrMJwQul1himH0+PQlwMbvrQOyeoqylKmf/qed2QbelO/qV+fqCxdRFdZfRkXhQAzu0/XqgbwmgVsAHZyM2U2Ro5EpbYpPpvQ1j20BhFo/HJh0rzaFTCOZSz4bgMY+sSYeGMG6YrJNdu2pNv7u7exhfO2pia6kX8BHdQJmhf/R2kRoTRMavYAkgaF0jAGcjjdtQkpqw/11RLlB0VrQg5MCIADxc+eFeYBHEaW2nf5MHRKE5yIsOnUmDK+5GH8+LEFbOm4hxPORJ9za0StqC4uHeDPUMEQftkq5XbgmqXa4gcM=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:VI1PR04MB6960.eurprd04.prod.outlook.com; PTR:; CAT:NONE;\n SFS:(4636009)(366004)(1006002)(8936002)(66556008)(5660300002)(6666004)(36756003)(26005)(55236004)(508600001)(2906002)(66476007)(38350700002)(38100700002)(8676002)(83380400001)(6916009)(1076003)(52116002)(7696005)(316002)(4326008)(956004)(186003)(2616005)(66946007)(6486002)(86362001)(110426009);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n f7rOvsyLx/0Q8vbJHZ4TRO/HflYtOnIuJT1bkGb9d0Llrq1UvZkw3ySh40cMq1DUEylb4K5lO9i3DzLMxRKLPUzVkyRfuikCtqDj/t5fArEE0BcdSzHqHWkhe0LawCBQgAn9E2JgCPnKkPLUSAqE5tOZrP4G5l+ju2t2BR9fW0+0TmuztERMKN7gAwCKrKGWQMMyMqwtsFDRmTDkCa1cBatD8kyY3zzpnXZ/gGYAfJ19iKqnrJMeDQD6bHWemLPZ+rddAEWDKJSiWEiNF0IVdydR9JJex30DFmQxjNVdNgwqGd+tw3FuKTRn9HKYvbjcEJoMofu6L1q3UOdJA1X3zLQt5rf66bJWnmyPGuwm28FlKuP6XR1FU9KrIR3yhzlG5dsuOdHnvABbNq0cI+aQPMyCYDh48g81u1LEtchoIOtt+MeKXgXrld+cj2pC01lS73hkYNaQAd/03pUQgLtGRbmg+CXslJK8uVhZb5uhuJ8B31kkO/trlEMkmhEVcovG/Qgq1HHyiTvotpqdZ1DjiFZYIkRAfeF8/88AmovRNWnM8XQunwNP5CItW5gD7xOuZ/gvo3EqECGz2qTawfPxrqvyrcrmY7BQebNADR4KMf7nM0TBQJJeEnRl5AYh2BlBbNsmPPzYKFZCJQZ0pPgrt5z3S/bxjQcziKDBVPe0oZ1V3HEUGjMwlbVwCX3C38vPfCSJlIZonzDFlTxFRKuyYsYhOcC4/TF71KNNmU78HR/YrLgmSam0+IblFr9f1FJLR/EOwEpVAOu2Qx9hBxSQqW1X5G9vRpw+oBAIxZV9FRl3lg59PRVB6KCK2DiDDmM4v40Qqh4o8RUxJfPjVqFW6HfeWXb/qtQTrmbIUucJOfKTJ4tJG1qnDe+F7+WEQefEChYANxN73Jxh28VVJSv1i2qQj31eGzanWBKblZ2SHyj5qr5BS0jtjvSex2eKbCW9Q0AQ9kRNVPfYermjJA++CvZaS6IC6PtRzuP2FwRw1Idt6nwCIhFV+KI7VblykVZgD/21cyt8SoluytyjW8r67UeiV6WSwajjcu+O+VMFyu7kO5YM44/WAX/x5PfINYabIHZJp8eKTzJLzylpVJj/ily/phPMz+FgdFs+f3PTSfVCMX/c3pOckjwOCjbDh/LSZS1YOBSiv6ZBviELcBSWc0Gckx8XXzYqPGDAF2BB8cCqQOFBMmVszA29cNwtS/vwq4NTnVqed1LgwHs7Bo0IhA4WqhL9rdlxoVAoVes8f4VM8fO4qoGWvVOGsB+/LXCAR9OU4QyA/NsNHdK/6FAnbPTFWeYIHicUDeFj4pVo3c4SronGCh6rWChV81igRGL3cj8nPhuwIYXPRspJVlVpTZvfTcYmBgi2gwPJ7tv6iuGDYyTibEiSXD6A12uGiRpd2rH5PnfO3iTf46Y+nJ7dj2ioa4OHwBfYoTO4MXqx033QnunH+1+jiJLac9enW8TWgUV3NsqQJjClXEeWZuAmWelR5+ie+ysrQNha0Z0bpdcfKxioMOL5n050iNBRMsDIZTfvh49EVjvAjtxjMaTIsBS/fzuzDYVH0hiDiG7zxS8=", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1af7620f-f4b5-4646-9bc3-08d9a2973420", "X-MS-Exchange-CrossTenant-AuthSource": "VI1PR04MB6960.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Nov 2021 09:07:35.0558 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n yTHZZsPYJ8S7KYerpdw3QdorbtpYtu4zuPwkuQDLuuSi8axOvHarNBd5DDzTjBoC", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "VE1PR04MB6495", "Subject": "[dpdk-dev] [PATCH v3 4/7] dma/dpaa: support basic operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch support basic DMA operations which includes\ndevice capability and channel setup.\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\n---\n drivers/dma/dpaa/dpaa_qdma.c | 204 +++++++++++++++++++++++++++++++++++\n drivers/dma/dpaa/dpaa_qdma.h | 6 ++\n 2 files changed, 210 insertions(+)", "diff": "diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c\nindex c3255dc0c7..e59cd36872 100644\n--- a/drivers/dma/dpaa/dpaa_qdma.c\n+++ b/drivers/dma/dpaa/dpaa_qdma.c\n@@ -8,6 +8,19 @@\n #include \"dpaa_qdma.h\"\n #include \"dpaa_qdma_logs.h\"\n \n+static inline void\n+qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr)\n+{\n+\tccdf->addr_hi = upper_32_bits(addr);\n+\tccdf->addr_lo = rte_cpu_to_le_32(lower_32_bits(addr));\n+}\n+\n+static inline void\n+qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len)\n+{\n+\tcsgf->cfg = rte_cpu_to_le_32(len & QDMA_SG_LEN_MASK);\n+}\n+\n static inline int\n ilog2(int x)\n {\n@@ -91,6 +104,77 @@ fsl_qdma_free_chan_resources(struct fsl_qdma_chan *fsl_chan)\n \tfsl_qdma->desc_allocated--;\n }\n \n+/*\n+ * Pre-request command descriptor and compound S/G for enqueue.\n+ */\n+static int\n+fsl_qdma_pre_request_enqueue_comp_sd_desc(\n+\t\t\t\t\tstruct fsl_qdma_queue *queue,\n+\t\t\t\t\tint size, int aligned)\n+{\n+\tstruct fsl_qdma_comp *comp_temp, *_comp_temp;\n+\tstruct fsl_qdma_sdf *sdf;\n+\tstruct fsl_qdma_ddf *ddf;\n+\tstruct fsl_qdma_format *csgf_desc;\n+\tint i;\n+\n+\tfor (i = 0; i < (int)(queue->n_cq + COMMAND_QUEUE_OVERFLLOW); i++) {\n+\t\tcomp_temp = rte_zmalloc(\"qdma: comp temp\",\n+\t\t\t\t\tsizeof(*comp_temp), 0);\n+\t\tif (!comp_temp)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tcomp_temp->virt_addr =\n+\t\tdma_pool_alloc(size, aligned, &comp_temp->bus_addr);\n+\t\tif (!comp_temp->virt_addr) {\n+\t\t\trte_free(comp_temp);\n+\t\t\tgoto fail;\n+\t\t}\n+\n+\t\tcomp_temp->desc_virt_addr =\n+\t\tdma_pool_alloc(size, aligned, &comp_temp->desc_bus_addr);\n+\t\tif (!comp_temp->desc_virt_addr) {\n+\t\t\trte_free(comp_temp->virt_addr);\n+\t\t\trte_free(comp_temp);\n+\t\t\tgoto fail;\n+\t\t}\n+\n+\t\tmemset(comp_temp->virt_addr, 0, FSL_QDMA_COMMAND_BUFFER_SIZE);\n+\t\tmemset(comp_temp->desc_virt_addr, 0,\n+\t\t FSL_QDMA_DESCRIPTOR_BUFFER_SIZE);\n+\n+\t\tcsgf_desc = (struct fsl_qdma_format *)comp_temp->virt_addr + 1;\n+\t\tsdf = (struct fsl_qdma_sdf *)comp_temp->desc_virt_addr;\n+\t\tddf = (struct fsl_qdma_ddf *)comp_temp->desc_virt_addr + 1;\n+\t\t/* Compound Command Descriptor(Frame List Table) */\n+\t\tqdma_desc_addr_set64(csgf_desc, comp_temp->desc_bus_addr);\n+\t\t/* It must be 32 as Compound S/G Descriptor */\n+\t\tqdma_csgf_set_len(csgf_desc, 32);\n+\t\t/* Descriptor Buffer */\n+\t\tsdf->cmd = rte_cpu_to_le_32(FSL_QDMA_CMD_RWTTYPE <<\n+\t\t\t FSL_QDMA_CMD_RWTTYPE_OFFSET);\n+\t\tddf->cmd = rte_cpu_to_le_32(FSL_QDMA_CMD_RWTTYPE <<\n+\t\t\t FSL_QDMA_CMD_RWTTYPE_OFFSET);\n+\t\tddf->cmd |= rte_cpu_to_le_32(FSL_QDMA_CMD_LWC <<\n+\t\t\t\tFSL_QDMA_CMD_LWC_OFFSET);\n+\n+\t\tlist_add_tail(&comp_temp->list, &queue->comp_free);\n+\t}\n+\n+\treturn 0;\n+\n+fail:\n+\tlist_for_each_entry_safe(comp_temp, _comp_temp,\n+\t\t\t\t &queue->comp_free, list) {\n+\t\tlist_del(&comp_temp->list);\n+\t\trte_free(comp_temp->virt_addr);\n+\t\trte_free(comp_temp->desc_virt_addr);\n+\t\trte_free(comp_temp);\n+\t}\n+\n+\treturn -ENOMEM;\n+}\n+\n static struct fsl_qdma_queue\n *fsl_qdma_alloc_queue_resources(struct fsl_qdma_engine *fsl_qdma)\n {\n@@ -335,6 +419,84 @@ fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)\n \treturn 0;\n }\n \n+static int\n+fsl_qdma_alloc_chan_resources(struct fsl_qdma_chan *fsl_chan)\n+{\n+\tstruct fsl_qdma_queue *fsl_queue = fsl_chan->queue;\n+\tstruct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;\n+\tint ret;\n+\n+\tif (fsl_queue->count++)\n+\t\tgoto finally;\n+\n+\tINIT_LIST_HEAD(&fsl_queue->comp_free);\n+\tINIT_LIST_HEAD(&fsl_queue->comp_used);\n+\n+\tret = fsl_qdma_pre_request_enqueue_comp_sd_desc(fsl_queue,\n+\t\t\t\tFSL_QDMA_COMMAND_BUFFER_SIZE, 64);\n+\tif (ret) {\n+\t\tDPAA_QDMA_ERR(\n+\t\t\t\"failed to alloc dma buffer for comp descriptor\\n\");\n+\t\tgoto exit;\n+\t}\n+\n+finally:\n+\treturn fsl_qdma->desc_allocated++;\n+\n+exit:\n+\treturn -ENOMEM;\n+}\n+\n+static int\n+dpaa_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *dev_info,\n+\t uint32_t info_sz)\n+{\n+#define DPAADMA_MAX_DESC 64\n+#define DPAADMA_MIN_DESC 64\n+\n+\tRTE_SET_USED(dev);\n+\tRTE_SET_USED(info_sz);\n+\n+\tdev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |\n+\t\t\t RTE_DMA_CAPA_MEM_TO_DEV |\n+\t\t\t RTE_DMA_CAPA_DEV_TO_DEV |\n+\t\t\t RTE_DMA_CAPA_DEV_TO_MEM |\n+\t\t\t RTE_DMA_CAPA_SILENT |\n+\t\t\t RTE_DMA_CAPA_OPS_COPY;\n+\tdev_info->max_vchans = 1;\n+\tdev_info->max_desc = DPAADMA_MAX_DESC;\n+\tdev_info->min_desc = DPAADMA_MIN_DESC;\n+\n+\treturn 0;\n+}\n+\n+static int\n+dpaa_get_channel(struct fsl_qdma_engine *fsl_qdma, uint16_t vchan)\n+{\n+\tu32 i, start, end;\n+\tint ret;\n+\n+\tstart = fsl_qdma->free_block_id * QDMA_QUEUES;\n+\tfsl_qdma->free_block_id++;\n+\n+\tend = start + 1;\n+\tfor (i = start; i < end; i++) {\n+\t\tstruct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];\n+\n+\t\tif (fsl_chan->free) {\n+\t\t\tfsl_chan->free = false;\n+\t\t\tret = fsl_qdma_alloc_chan_resources(fsl_chan);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\n+\t\t\tfsl_qdma->vchan_map[vchan] = i;\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\treturn -1;\n+}\n+\n static void\n dma_release(void *fsl_chan)\n {\n@@ -342,6 +504,45 @@ dma_release(void *fsl_chan)\n \tfsl_qdma_free_chan_resources((struct fsl_qdma_chan *)fsl_chan);\n }\n \n+static int\n+dpaa_qdma_configure(__rte_unused struct rte_dma_dev *dmadev,\n+\t\t __rte_unused const struct rte_dma_conf *dev_conf,\n+\t\t __rte_unused uint32_t conf_sz)\n+{\n+\treturn 0;\n+}\n+\n+static int\n+dpaa_qdma_start(__rte_unused struct rte_dma_dev *dev)\n+{\n+\treturn 0;\n+}\n+\n+static int\n+dpaa_qdma_close(__rte_unused struct rte_dma_dev *dev)\n+{\n+\treturn 0;\n+}\n+\n+static int\n+dpaa_qdma_queue_setup(struct rte_dma_dev *dmadev,\n+\t\t uint16_t vchan,\n+\t\t __rte_unused const struct rte_dma_vchan_conf *conf,\n+\t\t __rte_unused uint32_t conf_sz)\n+{\n+\tstruct fsl_qdma_engine *fsl_qdma = dmadev->data->dev_private;\n+\n+\treturn dpaa_get_channel(fsl_qdma, vchan);\n+}\n+\n+static struct rte_dma_dev_ops dpaa_qdma_ops = {\n+\t.dev_info_get\t\t = dpaa_info_get,\n+\t.dev_configure = dpaa_qdma_configure,\n+\t.dev_start = dpaa_qdma_start,\n+\t.dev_close = dpaa_qdma_close,\n+\t.vchan_setup\t\t = dpaa_qdma_queue_setup,\n+};\n+\n static int\n dpaa_qdma_init(struct rte_dma_dev *dmadev)\n {\n@@ -448,6 +649,9 @@ dpaa_qdma_probe(__rte_unused struct rte_dpaa_driver *dpaa_drv,\n \t}\n \n \tdpaa_dev->dmadev = dmadev;\n+\tdmadev->dev_ops = &dpaa_qdma_ops;\n+\tdmadev->device = &dpaa_dev->device;\n+\tdmadev->fp_obj->dev_private = dmadev->data->dev_private;\n \n \t/* Invoke PMD device initialization function */\n \tret = dpaa_qdma_init(dmadev);\ndiff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h\nindex c05620b740..f046167108 100644\n--- a/drivers/dma/dpaa/dpaa_qdma.h\n+++ b/drivers/dma/dpaa/dpaa_qdma.h\n@@ -10,6 +10,12 @@\n #define CORE_NUMBER 4\n #define RETRIES\t5\n \n+#ifndef GENMASK\n+#define BITS_PER_LONG\t(__SIZEOF_LONG__ * 8)\n+#define GENMASK(h, l) \\\n+\t\t(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))\n+#endif\n+\n #define FSL_QDMA_DMR\t\t\t0x0\n #define FSL_QDMA_DSR\t\t\t0x4\n #define FSL_QDMA_DEIER\t\t\t0xe00\n", "prefixes": [ "v3", "4/7" ] }