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GET /api/patches/103783/?format=api
{ "id": 103783, "url": "http://patches.dpdk.org/api/patches/103783/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211104175904.60696-3-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211104175904.60696-3-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211104175904.60696-3-bingz@nvidia.com", "date": "2021-11-04T17:59:04", "name": "[v4,2/2] net/mlx5: check delay drop settings in kernel driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cb51b0ec4d13ad52b222331558bc282f8e2e504b", "submitter": { "id": 1976, "url": "http://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211104175904.60696-3-bingz@nvidia.com/mbox/", "series": [ { "id": 20319, "url": "http://patches.dpdk.org/api/series/20319/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20319", "date": "2021-11-04T17:59:02", "name": "Add delay drop support for Rx queue", "version": 4, "mbox": "http://patches.dpdk.org/series/20319/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103783/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/103783/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 369F0A0C57;\n\tThu, 4 Nov 2021 18:59:45 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9FDB74278D;\n\tThu, 4 Nov 2021 18:59:35 +0100 (CET)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2052.outbound.protection.outlook.com [40.107.94.52])\n by mails.dpdk.org (Postfix) with ESMTP id 9942042766\n for <dev@dpdk.org>; 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dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, <thomas@monjalon.net>,\n <orika@nvidia.com>", "Date": "Thu, 4 Nov 2021 19:59:04 +0200", "Message-ID": "<20211104175904.60696-3-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20211104175904.60696-1-bingz@nvidia.com>", "References": "<20211104112644.17278-1-bingz@nvidia.com>\n <20211104175904.60696-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "9e29270a-ab13-48e7-1a2f-08d99fbcda3b", "X-MS-TrafficTypeDiagnostic": "SN1PR12MB2590:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <SN1PR12MB25901D49E9BFCB61A407FC58D08D9@SN1PR12MB2590.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:1360;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n x3HBFE2mRCxjAbM9goxu0rfcCXvm8feax59ozGOQ8obt4ywoyqsRWcBSZqPMW9riIAHooU26jscdVhWkv+Fy9ZyXi2BS+/Ycm1U27g74MaDVjEGl3wqdnEaPFd9OZn7J3SCTphM84uY8pt8+qN/TyHMWXoYRc5SJUG+InxQ5edQLHqw2wtdZes5JJjhS4rPW8sG1MIRFdXWHWDlXNCJ3u8VEtsVtArCbeKhOXU3/cwpGQVwsFITa9nfxVjWzQi4L/vda5SnNgt62w2sT73FwJMOtZay9k9mhGuoH27z6HHAJH+V+6I9v8LPUnKw9Z29ritnk7d1SfejrGI/P+4tNKThDfwJ4Ik5tPKhNUylDbxf/xtJb29l9BmxdWP8H9a2SovFGm6G0zITf4VtE7Y7PxL43oZFcHt1kDZsGfiEu7zoN2b2j3rfX7Qe6VgwEwipcYPv1ugfUwC3wUYcOE9ddfTt4O/SEkSWlJzqziWhGgyvi+MJxAadY6OMu6zCALJmgTJvnC4XZx9YBPC/YDREgnuWlVTu6Nc4OEu1NuxYbOwD+kowIRKt+l1iRujmrtO8Rh1fx1S7BSyuLh19PH8oSeepo4t2FZ9idf7/am2scxQwpLs5UfW5PnKtkxDA2Z+xTX/75tgDsTgh6OMgIz9qT/P2O1gGuPyUDpuRO3IGtHctXcY6GuA8wl6ZlVCXS6ziowEkofmilIEE88G/6vJp/bA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(2906002)(47076005)(82310400003)(86362001)(54906003)(36860700001)(316002)(110136005)(7696005)(4326008)(7636003)(70206006)(70586007)(8676002)(16526019)(186003)(426003)(26005)(8936002)(55016002)(6666004)(83380400001)(5660300002)(1076003)(356005)(508600001)(2616005)(36756003)(336012)(107886003)(6286002)(6636002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Nov 2021 17:59:31.0811 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9e29270a-ab13-48e7-1a2f-08d99fbcda3b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT010.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN1PR12MB2590", "Subject": "[dpdk-dev] [PATCH v4 2/2] net/mlx5: check delay drop settings in\n kernel driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The delay drop is the common feature managed on per device basis\nand the kernel driver is responsible one for the initialization and\nrearming.\n\nBy default, the timeout value is set to activate the delay drop when\nthe driver is loaded.\n\nA private flag \"dropless_rq\" is used to control the rearming. Only\nwhen it is on, the rearming will be handled once received a timeout\nevent. Or else, the delay drop will be deactivated after the first\ntimeout occurs and all the Rx queues won't have this feature.\n\nThe PMD is trying to query this flag and warn the application when\nsome queues are created with delay drop but the flag is off.\n\nThe documents are also updated in this commit.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 26 +++++\n doc/guides/rel_notes/release_21_11.rst | 1 +\n drivers/net/mlx5/linux/mlx5_ethdev_os.c | 111 ++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_trigger.c | 18 ++++\n drivers/net/mlx5/windows/mlx5_ethdev_os.c | 17 ++++\n 6 files changed, 174 insertions(+)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 824971d89a..006896375f 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -1129,6 +1129,27 @@ Driver options\n \n By default, the PMD will set this value to 1.\n \n+- ``delay_drop_en`` parameter [int]\n+\n+ Bitmask value for the Rx queue delay drop attribute. Bit 0 is used for standard\n+ Rx queue and bit 1 is used for hairpin Rx queue.\n+ By default, the delay drop will be enabled for all hairpin Rx queues (if any)\n+ and disabled for all standard Rx queues. It will be ignored if the NIC does\n+ not support the attribute.\n+ A timeout value is set in the driver to control the waiting time before dropping\n+ a packet when there is no WQE available on a delay drop Rx queue. Once the timer\n+ is expired, the delay drop will be deactivated for all queues. To re-activeate it,\n+ a rearming is needed and now it is part of the kernel driver.\n+\n+ To enable / disable the delay drop rearming, the private flag ``dropless_rq`` can\n+ be set and queried via ethtool:\n+\n+ - ethtool --set-priv-flags <netdev> dropless_rq on (/ off)\n+ - ethtool --show-priv-flags <netdev>\n+\n+ The configuration flag is global per PF and can only be set on the PF, once it is on,\n+ all the VFs', SFs' and representors' Rx queues will share the timer and rearming.\n+\n .. _mlx5_firmware_config:\n \n Firmware configuration\n@@ -1803,6 +1824,11 @@ Supported hardware offloads\n | | | | | rdma-core 35 |\n | | | | | ConnectX-6 Dx |\n +-----------------------+-----------------+-----------------+\n+ | Rxq Delay drop | | DPDK 21.11 | | DPDK 21.11 |\n+ | | | OFED 5.5 | | OFED 5.5 |\n+ | | | N/A | | N/A |\n+ | | | ConnectX-5 | | ConnectX-5 |\n+ +-----------------------+-----------------+-----------------+\n \n .. table:: Minimal SW/HW versions for shared action offload\n :name: sact\ndiff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst\nindex 13d8330873..76d18aeb6b 100644\n--- a/doc/guides/rel_notes/release_21_11.rst\n+++ b/doc/guides/rel_notes/release_21_11.rst\n@@ -191,6 +191,7 @@ New Features\n * Added implicit mempool registration to avoid data path hiccups (opt-out).\n * Added NIC offloads for the PMD on Windows (TSO, VLAN strip, CRC keep).\n * Added socket direct mode bonding support.\n+ * Added delay drop support for Rx queue.\n \n * **Updated Solarflare network PMD.**\n \ndiff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c\nindex 9d0e491d0c..c19825ee52 100644\n--- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c\n@@ -1630,3 +1630,114 @@ mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN])\n \tmemcpy(mac, request.ifr_hwaddr.sa_data, RTE_ETHER_ADDR_LEN);\n \treturn 0;\n }\n+\n+/*\n+ * Query dropless_rq private flag value provided by ETHTOOL.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ *\n+ * @return\n+ * - 0 on success, flag is not set.\n+ * - 1 on success, flag is set.\n+ * - negative errno value otherwise and rte_errno is set.\n+ */\n+int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev)\n+{\n+\tstruct {\n+\t\tstruct ethtool_sset_info hdr;\n+\t\tuint32_t buf[1];\n+\t} sset_info;\n+\tstruct ethtool_drvinfo drvinfo;\n+\tstruct ifreq ifr;\n+\tstruct ethtool_gstrings *strings = NULL;\n+\tstruct ethtool_value flags;\n+\tconst int32_t flag_len = sizeof(flags.data) * CHAR_BIT;\n+\tint32_t str_sz;\n+\tint32_t len;\n+\tint32_t i;\n+\tint ret;\n+\n+\tsset_info.hdr.cmd = ETHTOOL_GSSET_INFO;\n+\tsset_info.hdr.reserved = 0;\n+\tsset_info.hdr.sset_mask = 1ULL << ETH_SS_PRIV_FLAGS;\n+\tifr.ifr_data = (caddr_t)&sset_info;\n+\tret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);\n+\tif (!ret) {\n+\t\tconst uint32_t *sset_lengths = sset_info.hdr.data;\n+\n+\t\tlen = sset_info.hdr.sset_mask ? sset_lengths[0] : 0;\n+\t} else if (ret == -EOPNOTSUPP) {\n+\t\tdrvinfo.cmd = ETHTOOL_GDRVINFO;\n+\t\tifr.ifr_data = (caddr_t)&drvinfo;\n+\t\tret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(WARNING, \"port %u cannot get the driver info\",\n+\t\t\t\tdev->data->port_id);\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tlen = *(uint32_t *)((char *)&drvinfo +\n+\t\t\toffsetof(struct ethtool_drvinfo, n_priv_flags));\n+\t} else {\n+\t\tDRV_LOG(WARNING, \"port %u cannot get the sset info\",\n+\t\t\tdev->data->port_id);\n+\t\tgoto exit;\n+\t}\n+\tif (!len) {\n+\t\tDRV_LOG(WARNING, \"port %u does not have private flag\",\n+\t\t\tdev->data->port_id);\n+\t\trte_errno = EOPNOTSUPP;\n+\t\tret = -rte_errno;\n+\t\tgoto exit;\n+\t} else if (len > flag_len) {\n+\t\tDRV_LOG(WARNING, \"port %u maximal private flags number is %d\",\n+\t\t\tdev->data->port_id, flag_len);\n+\t\tlen = flag_len;\n+\t}\n+\tstr_sz = ETH_GSTRING_LEN * len;\n+\tstrings = (struct ethtool_gstrings *)\n+\t\t mlx5_malloc(0, str_sz + sizeof(struct ethtool_gstrings), 0,\n+\t\t\t SOCKET_ID_ANY);\n+\tif (!strings) {\n+\t\tDRV_LOG(WARNING, \"port %u unable to allocate memory for\"\n+\t\t\t\" private flags\", dev->data->port_id);\n+\t\trte_errno = ENOMEM;\n+\t\tret = -rte_errno;\n+\t\tgoto exit;\n+\t}\n+\tstrings->cmd = ETHTOOL_GSTRINGS;\n+\tstrings->string_set = ETH_SS_PRIV_FLAGS;\n+\tstrings->len = len;\n+\tifr.ifr_data = (caddr_t)strings;\n+\tret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);\n+\tif (ret) {\n+\t\tDRV_LOG(WARNING, \"port %u unable to get private flags strings\",\n+\t\t\tdev->data->port_id);\n+\t\tgoto exit;\n+\t}\n+\tfor (i = 0; i < len; i++) {\n+\t\tstrings->data[(i + 1) * ETH_GSTRING_LEN - 1] = 0;\n+\t\tif (!strcmp((const char *)strings->data + i * ETH_GSTRING_LEN,\n+\t\t\t \"dropless_rq\"))\n+\t\t\tbreak;\n+\t}\n+\tif (i == len) {\n+\t\tDRV_LOG(WARNING, \"port %u does not support dropless_rq\",\n+\t\t\tdev->data->port_id);\n+\t\trte_errno = EOPNOTSUPP;\n+\t\tret = -rte_errno;\n+\t\tgoto exit;\n+\t}\n+\tflags.cmd = ETHTOOL_GPFLAGS;\n+\tifr.ifr_data = (caddr_t)&flags;\n+\tret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);\n+\tif (ret) {\n+\t\tDRV_LOG(WARNING, \"port %u unable to get private flags status\",\n+\t\t\tdev->data->port_id);\n+\t\tgoto exit;\n+\t}\n+\tret = !!(flags.data & (1U << i));\n+exit:\n+\tmlx5_free(strings);\n+\treturn ret;\n+}\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex b2022f3300..9307a4f95b 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1602,6 +1602,7 @@ int mlx5_os_read_dev_stat(struct mlx5_priv *priv,\n int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);\n int mlx5_os_get_stats_n(struct rte_eth_dev *dev);\n void mlx5_os_stats_init(struct rte_eth_dev *dev);\n+int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev);\n \n /* mlx5_mac.c */\n \ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex a3e62e9533..0ecc530043 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -1129,6 +1129,24 @@ mlx5_dev_start(struct rte_eth_dev *dev)\n \t\t\tdev->data->port_id, strerror(rte_errno));\n \t\tgoto error;\n \t}\n+\tif (priv->config.std_delay_drop || priv->config.hp_delay_drop) {\n+\t\tif (!priv->config.vf && !priv->config.sf &&\n+\t\t !priv->representor) {\n+\t\t\tret = mlx5_get_flag_dropless_rq(dev);\n+\t\t\tif (ret < 0)\n+\t\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\t\"port %u cannot query dropless flag\",\n+\t\t\t\t\tdev->data->port_id);\n+\t\t\telse if (!ret)\n+\t\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\t\"port %u dropless_rq OFF, no rearming\",\n+\t\t\t\t\tdev->data->port_id);\n+\t\t} else {\n+\t\t\tDRV_LOG(DEBUG,\n+\t\t\t\t\"port %u doesn't support dropless_rq flag\",\n+\t\t\t\tdev->data->port_id);\n+\t\t}\n+\t}\n \tret = mlx5_rxq_start(dev);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"port %u Rx queue allocation failed: %s\",\ndiff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c\nindex fddc7a6b12..359f73df7c 100644\n--- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c\n@@ -389,3 +389,20 @@ mlx5_is_removed(struct rte_eth_dev *dev)\n \t\treturn 1;\n \treturn 0;\n }\n+\n+/*\n+ * Query dropless_rq private flag value provided by ETHTOOL.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ *\n+ * @return\n+ * - 0 on success, flag is not set.\n+ * - 1 on success, flag is set.\n+ * - negative errno value otherwise and rte_errno is set.\n+ */\n+int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+\treturn -ENOTSUP;\n+}\n", "prefixes": [ "v4", "2/2" ] }