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GET /api/patches/103774/?format=api
{ "id": 103774, "url": "http://patches.dpdk.org/api/patches/103774/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211104145548.59747-3-thomas@monjalon.net/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211104145548.59747-3-thomas@monjalon.net>", "list_archive_url": "https://inbox.dpdk.org/dev/20211104145548.59747-3-thomas@monjalon.net", "date": "2021-11-04T14:55:47", "name": "[v24,2/3] examples/qos_sched: support PIE congestion management", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c2a296a3335dd6e41e9d3e3362f88274c7dc895d", "submitter": { "id": 685, "url": "http://patches.dpdk.org/api/people/685/?format=api", "name": "Thomas Monjalon", "email": "thomas@monjalon.net" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211104145548.59747-3-thomas@monjalon.net/mbox/", "series": [ { "id": 20315, "url": "http://patches.dpdk.org/api/series/20315/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20315", "date": "2021-11-04T14:55:45", "name": "Add PIE support for HQoS library", "version": 24, "mbox": "http://patches.dpdk.org/series/20315/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103774/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/103774/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 516D9A0C47;\n\tThu, 4 Nov 2021 15:56:22 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 83D3E42766;\n\tThu, 4 Nov 2021 15:56:07 +0100 (CET)", "from wout1-smtp.messagingengine.com (wout1-smtp.messagingengine.com\n [64.147.123.24]) by mails.dpdk.org (Postfix) with ESMTP id 56D2742720\n for <dev@dpdk.org>; Thu, 4 Nov 2021 15:56:06 +0100 (CET)", "from compute4.internal (compute4.nyi.internal [10.202.2.44])\n by mailout.west.internal (Postfix) with ESMTP id 18DD53201C81;\n Thu, 4 Nov 2021 10:56:04 -0400 (EDT)", "from mailfrontend2 ([10.202.2.163])\n by compute4.internal (MEProxy); Thu, 04 Nov 2021 10:56:04 -0400", "by mail.messagingengine.com (Postfix) with ESMTPA; Thu,\n 4 Nov 2021 10:56:02 -0400 (EDT)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding; s=fm2; bh=XGElD1kdx1FgF\n GY89uwug+Ddpg/5E68EreXuvSwdG1Q=; b=nM8hhqZik00XY6mlxtUba6akCIr+T\n VWp3bHpz9NFvboMZMppKD7gDHqzfqO+jBCfylM4cWjK28z7w6hk5XrC+AAyL0dJm\n EeLwySfNn1Hm9SBAMZo2DsPUQItSk0WL5zIpd61FX7Fv+82PV3H7LbWQyp61I16p\n hngbZbzqIgf1NKKh7ZeVP2U0ru168lD+jnb9Evb55uyH6ei0r7cE3EFATgHJMWY9\n dkC27hSFgEkvJx8dw40nH37a8bu7eBYZ6K5+0oFQwsQVn5L2LDwwhUWObQeGH+0z\n O9TK3wq+6yRnmq5qUJilfck+6DEn6M3hcOuJM5uWH+5vMK/36//LKe+9w==", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=\n messagingengine.com; h=cc:content-transfer-encoding:date:from\n :in-reply-to:message-id:mime-version:references:subject:to\n :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=\n fm1; bh=XGElD1kdx1FgFGY89uwug+Ddpg/5E68EreXuvSwdG1Q=; b=BGO6wLuh\n qX6JBXmVjykP+jDDI0VC+4qm61HXdU5OemGQc3j7dNnNUUejThpig1DyawCfGdyW\n 6m6l4Rmj8n+f/uCfgo4RQ6l3vs8Xdv+67UVn3hVZxukzuw3DziVvibPHGJls5V2H\n W2FL6OkeDtbpgn4BvoSh2Y6qfSlsgoNXAa67xAuzH2p3vmC/154MAUZb3DR0I+TU\n JVN/J2xVinem1WBavb+DRUzPoDs+h83ms8ee08/sixqv38yK/p/AfbGSy5fCNv0O\n VURwzDZAhWREaW2FcBhUm98sMfeJTDa3VtpfNZsSnEZtn+OqsNnZkYxcXbLZb0iG\n TG23fKk7cvgNVw==" ], "X-ME-Sender": "<xms:g_SDYTrpsPCtgzVD0DmzA74-Yj50KoV3tJAs3r2t1f8IrVqgYaiqBg>\n <xme:g_SDYdqFSwLfogCG7rHl3BYHHm4f-mNpyDqKPq19XSjeDbMs8CdTSsCh9LJLY0HmU\n WSP0-dioldOSoxacQ>", "X-ME-Received": "\n <xmr:g_SDYQMywjwPn9a_YfwFeIYSjSvkKL9cRm-aCTeeeHZYCNSVsMoIQBhvUdx0ro_eMeOFybRqkzadvwlz-IoCmCkJp8G2hKs>", "X-ME-Proxy-Cause": "\n gggruggvucftvghtrhhoucdtuddrgedvuddrtdeggdeihecutefuodetggdotefrodftvf\n curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu\n uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc\n fjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepvfhhohhmrghs\n ucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenucggtf\n frrghtthgvrhhnpedvhefgiedvjeegtdevheefhfetleefgfeivefgffevfeejgedtgfeu\n tdehtdegveenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh\n hmpehthhhomhgrshesmhhonhhjrghlohhnrdhnvght", "X-ME-Proxy": "<xmx:g_SDYW5pRVG8f2u8MFfjDHvVCFgIMvGBlsAknt9nv8Y3mBgozD2vtw>\n <xmx:g_SDYS588sjkMrfHe2FIZ6DW5SbXGV58eTpPD7k8C6LYP8I8hKCnRw>\n <xmx:g_SDYejPHkqLsXK4CeJ3-c2C9nlirkNt9uaLzW0CrPzlVHEUVrGwHw>\n <xmx:g_SDYYlKSrs_2_-z99q5aQ1LlCYNM5HuGOXJn_RL1YDroh6ntCgMTw>", "From": "Thomas Monjalon <thomas@monjalon.net>", "To": "dev@dpdk.org", "Cc": "megha.ajmera@intel.com,\n Wojciech Liguzinski <wojciechx.liguzinski@intel.com>,\n Cristian Dumitrescu <cristian.dumitrescu@intel.com>,\n Jasvinder Singh <jasvinder.singh@intel.com>", "Date": "Thu, 4 Nov 2021 15:55:47 +0100", "Message-Id": "<20211104145548.59747-3-thomas@monjalon.net>", "X-Mailer": "git-send-email 2.33.0", "In-Reply-To": "<20211104145548.59747-1-thomas@monjalon.net>", "References": "<20211104104918.490051-1-wojciechx.liguzinski@intel.com>\n <20211104145548.59747-1-thomas@monjalon.net>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v24 2/3] examples/qos_sched: support PIE\n congestion management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Wojciech Liguzinski <wojciechx.liguzinski@intel.com>\n\npatch add support enable PIE or RED by\nparsing config file.\n\nSigned-off-by: Wojciech Liguzinski <wojciechx.liguzinski@intel.com>\nAcked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\nAcked-by: Jasvinder Singh <jasvinder.singh@intel.com>\n---\n examples/qos_sched/cfg_file.c | 121 +++++++++++++++-----\n examples/qos_sched/cfg_file.h | 5 +\n examples/qos_sched/init.c | 23 ++--\n examples/qos_sched/main.h | 3 +\n examples/qos_sched/profile.cfg | 196 ++++++++++++++++++++++-----------\n 5 files changed, 245 insertions(+), 103 deletions(-)", "diff": "diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c\nindex 4bef887099..450482f07d 100644\n--- a/examples/qos_sched/cfg_file.c\n+++ b/examples/qos_sched/cfg_file.c\n@@ -229,6 +229,40 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,\n \treturn 0;\n }\n \n+#ifdef RTE_SCHED_CMAN\n+void set_subport_cman_params(struct rte_sched_subport_params *subport_p,\n+\t\t\t\t\tstruct rte_sched_cman_params cman_p)\n+{\n+\tint j, k;\n+\tsubport_p->cman_params->cman_mode = cman_p.cman_mode;\n+\n+\tfor (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {\n+\t\tif (subport_p->cman_params->cman_mode ==\n+\t\t\t\t\tRTE_SCHED_CMAN_RED) {\n+\t\t\tfor (k = 0; k < RTE_COLORS; k++) {\n+\t\t\t\tsubport_p->cman_params->red_params[j][k].min_th =\n+\t\t\t\t\tcman_p.red_params[j][k].min_th;\n+\t\t\t\tsubport_p->cman_params->red_params[j][k].max_th =\n+\t\t\t\t\tcman_p.red_params[j][k].max_th;\n+\t\t\t\tsubport_p->cman_params->red_params[j][k].maxp_inv =\n+\t\t\t\t\tcman_p.red_params[j][k].maxp_inv;\n+\t\t\t\tsubport_p->cman_params->red_params[j][k].wq_log2 =\n+\t\t\t\t\tcman_p.red_params[j][k].wq_log2;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tsubport_p->cman_params->pie_params[j].qdelay_ref =\n+\t\t\t\tcman_p.pie_params[j].qdelay_ref;\n+\t\t\tsubport_p->cman_params->pie_params[j].dp_update_interval =\n+\t\t\t\tcman_p.pie_params[j].dp_update_interval;\n+\t\t\tsubport_p->cman_params->pie_params[j].max_burst =\n+\t\t\t\tcman_p.pie_params[j].max_burst;\n+\t\t\tsubport_p->cman_params->pie_params[j].tailq_th =\n+\t\t\t\tcman_p.pie_params[j].tailq_th;\n+\t\t}\n+\t}\n+}\n+#endif\n+\n int\n cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)\n {\n@@ -243,24 +277,25 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \tn_active_queues = 0;\n \n #ifdef RTE_SCHED_CMAN\n-\tchar sec_name[CFG_NAME_LEN];\n-\tstruct rte_red_params red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];\n+\tstruct rte_sched_cman_params cman_params = {\n+\t\t.cman_mode = RTE_SCHED_CMAN_RED,\n+\t\t.red_params = { },\n+\t};\n \n-\tsnprintf(sec_name, sizeof(sec_name), \"red\");\n-\n-\tif (rte_cfgfile_has_section(cfg, sec_name)) {\n+\tif (rte_cfgfile_has_section(cfg, \"red\")) {\n+\t\tcman_params.cman_mode = RTE_SCHED_CMAN_RED;\n \n \t\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n \t\t\tchar str[32];\n \n-\t\t\t/* Parse WRED min thresholds */\n-\t\t\tsnprintf(str, sizeof(str), \"tc %d wred min\", i);\n-\t\t\tentry = rte_cfgfile_get_entry(cfg, sec_name, str);\n+\t\t\t/* Parse RED min thresholds */\n+\t\t\tsnprintf(str, sizeof(str), \"tc %d red min\", i);\n+\t\t\tentry = rte_cfgfile_get_entry(cfg, \"red\", str);\n \t\t\tif (entry) {\n \t\t\t\tchar *next;\n \t\t\t\t/* for each packet colour (green, yellow, red) */\n \t\t\t\tfor (j = 0; j < RTE_COLORS; j++) {\n-\t\t\t\t\tred_params[i][j].min_th\n+\t\t\t\t\tcman_params.red_params[i][j].min_th\n \t\t\t\t\t\t= (uint16_t)strtol(entry, &next, 10);\n \t\t\t\t\tif (next == NULL)\n \t\t\t\t\t\tbreak;\n@@ -268,14 +303,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \t\t\t\t}\n \t\t\t}\n \n-\t\t\t/* Parse WRED max thresholds */\n-\t\t\tsnprintf(str, sizeof(str), \"tc %d wred max\", i);\n+\t\t\t/* Parse RED max thresholds */\n+\t\t\tsnprintf(str, sizeof(str), \"tc %d red max\", i);\n \t\t\tentry = rte_cfgfile_get_entry(cfg, \"red\", str);\n \t\t\tif (entry) {\n \t\t\t\tchar *next;\n \t\t\t\t/* for each packet colour (green, yellow, red) */\n \t\t\t\tfor (j = 0; j < RTE_COLORS; j++) {\n-\t\t\t\t\tred_params[i][j].max_th\n+\t\t\t\t\tcman_params.red_params[i][j].max_th\n \t\t\t\t\t\t= (uint16_t)strtol(entry, &next, 10);\n \t\t\t\t\tif (next == NULL)\n \t\t\t\t\t\tbreak;\n@@ -283,14 +318,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \t\t\t\t}\n \t\t\t}\n \n-\t\t\t/* Parse WRED inverse mark probabilities */\n-\t\t\tsnprintf(str, sizeof(str), \"tc %d wred inv prob\", i);\n+\t\t\t/* Parse RED inverse mark probabilities */\n+\t\t\tsnprintf(str, sizeof(str), \"tc %d red inv prob\", i);\n \t\t\tentry = rte_cfgfile_get_entry(cfg, \"red\", str);\n \t\t\tif (entry) {\n \t\t\t\tchar *next;\n \t\t\t\t/* for each packet colour (green, yellow, red) */\n \t\t\t\tfor (j = 0; j < RTE_COLORS; j++) {\n-\t\t\t\t\tred_params[i][j].maxp_inv\n+\t\t\t\t\tcman_params.red_params[i][j].maxp_inv\n \t\t\t\t\t\t= (uint8_t)strtol(entry, &next, 10);\n \n \t\t\t\t\tif (next == NULL)\n@@ -299,14 +334,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \t\t\t\t}\n \t\t\t}\n \n-\t\t\t/* Parse WRED EWMA filter weights */\n-\t\t\tsnprintf(str, sizeof(str), \"tc %d wred weight\", i);\n+\t\t\t/* Parse RED EWMA filter weights */\n+\t\t\tsnprintf(str, sizeof(str), \"tc %d red weight\", i);\n \t\t\tentry = rte_cfgfile_get_entry(cfg, \"red\", str);\n \t\t\tif (entry) {\n \t\t\t\tchar *next;\n \t\t\t\t/* for each packet colour (green, yellow, red) */\n \t\t\t\tfor (j = 0; j < RTE_COLORS; j++) {\n-\t\t\t\t\tred_params[i][j].wq_log2\n+\t\t\t\t\tcman_params.red_params[i][j].wq_log2\n \t\t\t\t\t\t= (uint8_t)strtol(entry, &next, 10);\n \t\t\t\t\tif (next == NULL)\n \t\t\t\t\t\tbreak;\n@@ -315,6 +350,43 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \t\t\t}\n \t\t}\n \t}\n+\n+\tif (rte_cfgfile_has_section(cfg, \"pie\")) {\n+\t\tcman_params.cman_mode = RTE_SCHED_CMAN_PIE;\n+\n+\t\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n+\t\t\tchar str[32];\n+\n+\t\t\t/* Parse Queue Delay Ref value */\n+\t\t\tsnprintf(str, sizeof(str), \"tc %d qdelay ref\", i);\n+\t\t\tentry = rte_cfgfile_get_entry(cfg, \"pie\", str);\n+\t\t\tif (entry)\n+\t\t\t\tcman_params.pie_params[i].qdelay_ref =\n+\t\t\t\t\t(uint16_t) atoi(entry);\n+\n+\t\t\t/* Parse Max Burst value */\n+\t\t\tsnprintf(str, sizeof(str), \"tc %d max burst\", i);\n+\t\t\tentry = rte_cfgfile_get_entry(cfg, \"pie\", str);\n+\t\t\tif (entry)\n+\t\t\t\tcman_params.pie_params[i].max_burst =\n+\t\t\t\t\t(uint16_t) atoi(entry);\n+\n+\t\t\t/* Parse Update Interval Value */\n+\t\t\tsnprintf(str, sizeof(str), \"tc %d update interval\", i);\n+\t\t\tentry = rte_cfgfile_get_entry(cfg, \"pie\", str);\n+\t\t\tif (entry)\n+\t\t\t\tcman_params.pie_params[i].dp_update_interval =\n+\t\t\t\t\t(uint16_t) atoi(entry);\n+\n+\t\t\t/* Parse Tailq Threshold Value */\n+\t\t\tsnprintf(str, sizeof(str), \"tc %d tailq th\", i);\n+\t\t\tentry = rte_cfgfile_get_entry(cfg, \"pie\", str);\n+\t\t\tif (entry)\n+\t\t\t\tcman_params.pie_params[i].tailq_th =\n+\t\t\t\t\t(uint16_t) atoi(entry);\n+\n+\t\t}\n+\t}\n #endif /* RTE_SCHED_CMAN */\n \n \tfor (i = 0; i < MAX_SCHED_SUBPORTS; i++) {\n@@ -394,18 +466,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \t\t\t\t}\n \t\t\t}\n #ifdef RTE_SCHED_CMAN\n-\t\t\tfor (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {\n-\t\t\t\tfor (k = 0; k < RTE_COLORS; k++) {\n-\t\t\t\t\tsubport_params[i].red_params[j][k].min_th =\n-\t\t\t\t\t\tred_params[j][k].min_th;\n-\t\t\t\t\tsubport_params[i].red_params[j][k].max_th =\n-\t\t\t\t\t\tred_params[j][k].max_th;\n-\t\t\t\t\tsubport_params[i].red_params[j][k].maxp_inv =\n-\t\t\t\t\t\tred_params[j][k].maxp_inv;\n-\t\t\t\t\tsubport_params[i].red_params[j][k].wq_log2 =\n-\t\t\t\t\t\tred_params[j][k].wq_log2;\n-\t\t\t\t}\n-\t\t\t}\n+\t\t\tset_subport_cman_params(subport_params+i, cman_params);\n #endif\n \t\t}\n \t}\ndiff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h\nindex 0dc458aa71..1a9dce9db5 100644\n--- a/examples/qos_sched/cfg_file.h\n+++ b/examples/qos_sched/cfg_file.h\n@@ -12,6 +12,11 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);\n \n int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);\n \n+#ifdef RTE_SCHED_CMAN\n+void set_subport_cman_params(struct rte_sched_subport_params *subport_p,\n+\t\t\t\t\tstruct rte_sched_cman_params cman_p);\n+#endif\n+\n int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);\n \n int cfg_load_subport_profile(struct rte_cfgfile *cfg,\ndiff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c\nindex 3bdc653c69..3c1f0bc680 100644\n--- a/examples/qos_sched/init.c\n+++ b/examples/qos_sched/init.c\n@@ -203,15 +203,9 @@ static struct rte_sched_subport_profile_params\n \t},\n };\n \n-struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {\n-\t{\n-\t\t.n_pipes_per_subport_enabled = 4096,\n-\t\t.qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64},\n-\t\t.pipe_profiles = pipe_profiles,\n-\t\t.n_pipe_profiles = sizeof(pipe_profiles) /\n-\t\t\tsizeof(struct rte_sched_pipe_params),\n-\t\t.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,\n #ifdef RTE_SCHED_CMAN\n+struct rte_sched_cman_params cman_params = {\n+\t.cman_mode = RTE_SCHED_CMAN_RED,\n \t.red_params = {\n \t\t/* Traffic Class 0 Colors Green / Yellow / Red */\n \t\t[0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n@@ -278,6 +272,19 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {\n \t\t[12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n \t\t[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n \t},\n+};\n+#endif /* RTE_SCHED_CMAN */\n+\n+struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {\n+\t{\n+\t\t.n_pipes_per_subport_enabled = 4096,\n+\t\t.qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64},\n+\t\t.pipe_profiles = pipe_profiles,\n+\t\t.n_pipe_profiles = sizeof(pipe_profiles) /\n+\t\t\tsizeof(struct rte_sched_pipe_params),\n+\t\t.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,\n+#ifdef RTE_SCHED_CMAN\n+\t\t.cman_params = &cman_params,\n #endif /* RTE_SCHED_CMAN */\n \t},\n };\ndiff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h\nindex 0d6815ae69..915311bac8 100644\n--- a/examples/qos_sched/main.h\n+++ b/examples/qos_sched/main.h\n@@ -153,6 +153,9 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];\n extern uint32_t n_active_queues;\n \n extern struct rte_sched_port_params port_params;\n+#ifdef RTE_SCHED_CMAN\n+extern struct rte_sched_cman_params cman_params;\n+#endif\n extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];\n \n int app_parse_args(int argc, char **argv);\ndiff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg\nindex 4486d2799e..d4b21c0170 100644\n--- a/examples/qos_sched/profile.cfg\n+++ b/examples/qos_sched/profile.cfg\n@@ -76,68 +76,134 @@ tc 12 oversubscription weight = 1\n tc 12 wrr weights = 1 1 1 1\n \n ; RED params per traffic class and color (Green / Yellow / Red)\n-[red]\n-tc 0 wred min = 48 40 32\n-tc 0 wred max = 64 64 64\n-tc 0 wred inv prob = 10 10 10\n-tc 0 wred weight = 9 9 9\n-\n-tc 1 wred min = 48 40 32\n-tc 1 wred max = 64 64 64\n-tc 1 wred inv prob = 10 10 10\n-tc 1 wred weight = 9 9 9\n-\n-tc 2 wred min = 48 40 32\n-tc 2 wred max = 64 64 64\n-tc 2 wred inv prob = 10 10 10\n-tc 2 wred weight = 9 9 9\n-\n-tc 3 wred min = 48 40 32\n-tc 3 wred max = 64 64 64\n-tc 3 wred inv prob = 10 10 10\n-tc 3 wred weight = 9 9 9\n-\n-tc 4 wred min = 48 40 32\n-tc 4 wred max = 64 64 64\n-tc 4 wred inv prob = 10 10 10\n-tc 4 wred weight = 9 9 9\n-\n-tc 5 wred min = 48 40 32\n-tc 5 wred max = 64 64 64\n-tc 5 wred inv prob = 10 10 10\n-tc 5 wred weight = 9 9 9\n-\n-tc 6 wred min = 48 40 32\n-tc 6 wred max = 64 64 64\n-tc 6 wred inv prob = 10 10 10\n-tc 6 wred weight = 9 9 9\n-\n-tc 7 wred min = 48 40 32\n-tc 7 wred max = 64 64 64\n-tc 7 wred inv prob = 10 10 10\n-tc 7 wred weight = 9 9 9\n-\n-tc 8 wred min = 48 40 32\n-tc 8 wred max = 64 64 64\n-tc 8 wred inv prob = 10 10 10\n-tc 8 wred weight = 9 9 9\n-\n-tc 9 wred min = 48 40 32\n-tc 9 wred max = 64 64 64\n-tc 9 wred inv prob = 10 10 10\n-tc 9 wred weight = 9 9 9\n-\n-tc 10 wred min = 48 40 32\n-tc 10 wred max = 64 64 64\n-tc 10 wred inv prob = 10 10 10\n-tc 10 wred weight = 9 9 9\n-\n-tc 11 wred min = 48 40 32\n-tc 11 wred max = 64 64 64\n-tc 11 wred inv prob = 10 10 10\n-tc 11 wred weight = 9 9 9\n-\n-tc 12 wred min = 48 40 32\n-tc 12 wred max = 64 64 64\n-tc 12 wred inv prob = 10 10 10\n-tc 12 wred weight = 9 9 9\n+;[red]\n+;tc 0 wred min = 48 40 32\n+;tc 0 wred max = 64 64 64\n+;tc 0 wred inv prob = 10 10 10\n+;tc 0 wred weight = 9 9 9\n+\n+;tc 1 wred min = 48 40 32\n+;tc 1 wred max = 64 64 64\n+;tc 1 wred inv prob = 10 10 10\n+;tc 1 wred weight = 9 9 9\n+\n+;tc 2 wred min = 48 40 32\n+;tc 2 wred max = 64 64 64\n+;tc 2 wred inv prob = 10 10 10\n+;tc 2 wred weight = 9 9 9\n+\n+;tc 3 wred min = 48 40 32\n+;tc 3 wred max = 64 64 64\n+;tc 3 wred inv prob = 10 10 10\n+;tc 3 wred weight = 9 9 9\n+\n+;tc 4 wred min = 48 40 32\n+;tc 4 wred max = 64 64 64\n+;tc 4 wred inv prob = 10 10 10\n+;tc 4 wred weight = 9 9 9\n+\n+;tc 5 wred min = 48 40 32\n+;tc 5 wred max = 64 64 64\n+;tc 5 wred inv prob = 10 10 10\n+;tc 5 wred weight = 9 9 9\n+\n+;tc 6 wred min = 48 40 32\n+;tc 6 wred max = 64 64 64\n+;tc 6 wred inv prob = 10 10 10\n+;tc 6 wred weight = 9 9 9\n+\n+;tc 7 wred min = 48 40 32\n+;tc 7 wred max = 64 64 64\n+;tc 7 wred inv prob = 10 10 10\n+;tc 7 wred weight = 9 9 9\n+\n+;tc 8 wred min = 48 40 32\n+;tc 8 wred max = 64 64 64\n+;tc 8 wred inv prob = 10 10 10\n+;tc 8 wred weight = 9 9 9\n+\n+;tc 9 wred min = 48 40 32\n+;tc 9 wred max = 64 64 64\n+;tc 9 wred inv prob = 10 10 10\n+;tc 9 wred weight = 9 9 9\n+\n+;tc 10 wred min = 48 40 32\n+;tc 10 wred max = 64 64 64\n+;tc 10 wred inv prob = 10 10 10\n+;tc 10 wred weight = 9 9 9\n+\n+;tc 11 wred min = 48 40 32\n+;tc 11 wred max = 64 64 64\n+;tc 11 wred inv prob = 10 10 10\n+;tc 11 wred weight = 9 9 9\n+\n+;tc 12 wred min = 48 40 32\n+;tc 12 wred max = 64 64 64\n+;tc 12 wred inv prob = 10 10 10\n+;tc 12 wred weight = 9 9 9\n+\n+[pie]\n+tc 0 qdelay ref = 15\n+tc 0 max burst = 150\n+tc 0 update interval = 15\n+tc 0 tailq th = 64\n+\n+tc 1 qdelay ref = 15\n+tc 1 max burst = 150\n+tc 1 update interval = 15\n+tc 1 tailq th = 64\n+\n+tc 2 qdelay ref = 15\n+tc 2 max burst = 150\n+tc 2 update interval = 15\n+tc 2 tailq th = 64\n+\n+tc 3 qdelay ref = 15\n+tc 3 max burst = 150\n+tc 3 update interval = 15\n+tc 3 tailq th = 64\n+\n+tc 4 qdelay ref = 15\n+tc 4 max burst = 150\n+tc 4 update interval = 15\n+tc 4 tailq th = 64\n+\n+tc 5 qdelay ref = 15\n+tc 5 max burst = 150\n+tc 5 update interval = 15\n+tc 5 tailq th = 64\n+\n+tc 6 qdelay ref = 15\n+tc 6 max burst = 150\n+tc 6 update interval = 15\n+tc 6 tailq th = 64\n+\n+tc 7 qdelay ref = 15\n+tc 7 max burst = 150\n+tc 7 update interval = 15\n+tc 7 tailq th = 64\n+\n+tc 8 qdelay ref = 15\n+tc 8 max burst = 150\n+tc 8 update interval = 15\n+tc 8 tailq th = 64\n+\n+tc 9 qdelay ref = 15\n+tc 9 max burst = 150\n+tc 9 update interval = 15\n+tc 9 tailq th = 64\n+\n+tc 10 qdelay ref = 15\n+tc 10 max burst = 150\n+tc 10 update interval = 15\n+tc 10 tailq th = 64\n+\n+tc 11 qdelay ref = 15\n+tc 11 max burst = 150\n+tc 11 update interval = 15\n+tc 11 tailq th = 64\n+\n+tc 12 qdelay ref = 15\n+tc 12 max burst = 150\n+tc 12 update interval = 15\n+tc 12 tailq th = 64\n", "prefixes": [ "v24", "2/3" ] }