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GET /api/patches/103614/?format=api
{ "id": 103614, "url": "http://patches.dpdk.org/api/patches/103614/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211103075838.1486056-6-xuemingl@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211103075838.1486056-6-xuemingl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211103075838.1486056-6-xuemingl@nvidia.com", "date": "2021-11-03T07:58:29", "name": "[v3,05/14] net/mlx5: fix Rx queue memory allocation return value", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4173e7a4ffc389bf4798555a0191ff0f4feea076", "submitter": { "id": 1904, "url": "http://patches.dpdk.org/api/people/1904/?format=api", "name": "Xueming Li", "email": "xuemingl@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211103075838.1486056-6-xuemingl@nvidia.com/mbox/", "series": [ { "id": 20258, "url": "http://patches.dpdk.org/api/series/20258/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20258", "date": "2021-11-03T07:58:24", "name": "net/mlx5: support shared Rx queue", "version": 3, "mbox": "http://patches.dpdk.org/series/20258/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103614/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/103614/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 605D2A0C53;\n\tWed, 3 Nov 2021 08:59:52 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9AA0A41158;\n\tWed, 3 Nov 2021 08:59:48 +0100 (CET)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2077.outbound.protection.outlook.com [40.107.236.77])\n by mails.dpdk.org (Postfix) with ESMTP id 2D06B41143;\n Wed, 3 Nov 2021 08:59:47 +0100 (CET)", "from MWHPR12CA0031.namprd12.prod.outlook.com (2603:10b6:301:2::17)\n by BN7PR12MB2609.namprd12.prod.outlook.com (2603:10b6:408:28::33) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.18; 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dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Xueming Li <xuemingl@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<xuemingl@nvidia.com>, Lior Margalit <lmargalit@nvidia.com>,\n <akozyrev@nvidia.com>, <stable@dpdk.org>, Matan Azrad <matan@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Wed, 3 Nov 2021 15:58:29 +0800", "Message-ID": "<20211103075838.1486056-6-xuemingl@nvidia.com>", "X-Mailer": "git-send-email 2.33.0", "In-Reply-To": "<20211103075838.1486056-1-xuemingl@nvidia.com>", "References": "<20210727034204.20649-1-xuemingl@nvidia.com>\n <20211103075838.1486056-1-xuemingl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "11f2da48-b4c7-41e8-5d3b-08d99e9fe601", "X-MS-TrafficTypeDiagnostic": "BN7PR12MB2609:", "X-Microsoft-Antispam-PRVS": "\n <BN7PR12MB260986D72296513107888B8AA18C9@BN7PR12MB2609.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:660;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n V7sXvQFu5K8f5t3n5M4eH6dbQNWGHIaMEnORSR9nri2fE1VtzPtb/Ut8UmGmBf/r386c4F0Lyy8EipJ5LSMV2IbvDDQifj5e+qn25AVlCy+71V9CEUGH4vaMmptf6co0Dc8uyYMWH306wUFcpR9ZOOy+Jv6X3waN8SDhvGX4zptebOe0VuOPU9CTxmr7Mq/+MdqM9z988Y3o6Zq/Qi+zCbLyrMA4Cber4wS/1qKKqc08RHRJig7DwceYF8b8pgu79JlHu5nHQuh42bWkfcFSFNArwPsVbnc80ay73BSQ6mTF5wb+pHtdlYIb0hAKuEn7Jko0Kst5EjPLmfT9jKL3Hy1Xfb1q5B/L6BwqQjGq8r6pc6ffXPb9OLmzDBq6hsaFP6uZuRf5H+rXo3gFSLA3pspQR3hrH+MfjQcK0gfmAv/6RxoJ0boAyzOq67WW64XMeQtqt4eBlcs9mJkq+/jXHb26DwEYxmNjA/jtQZhza+YMUfQV4hYsDvJOU+QrJG3zZX9yCeCV2dRidXsB+9dUmPLHCqXrpUOmp8k6W/OrPAc7jOwT95vviQRX3bL7g8lP2C5VXqP5HT/qC5ol0apOMwxYHdXEEvcZ6seiiYbLxbfx3+4vV0T8JGbQ4QOZtfwA4fA8zqgtZ0GTsiDdv7/Feq0oJeehC6UxN3eMIHRVtaLrbI4H24HL5V27VXvczOowIX97M6WoObRqrvjiS8Y0Aw==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(82310400003)(70586007)(450100002)(7696005)(36860700001)(70206006)(6286002)(508600001)(6916009)(86362001)(26005)(107886003)(2616005)(426003)(336012)(55016002)(8936002)(186003)(16526019)(83380400001)(47076005)(1076003)(36756003)(54906003)(316002)(4326008)(2906002)(356005)(5660300002)(7636003)(6666004)(8676002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "03 Nov 2021 07:59:44.4394 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 11f2da48-b4c7-41e8-5d3b-08d99e9fe601", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT054.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN7PR12MB2609", "Subject": "[dpdk-dev] [PATCH v3 05/14] net/mlx5: fix Rx queue memory\n allocation return value", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "If error happened during Rx queue mbuf allocation, boolean value\nreturned. From description, return value should be error number.\n\nThis patch returns negative error number.\n\nFixes: 0f20acbf5eda (\"net/mlx5: implement vectorized MPRQ burst\")\nCc: akozyrev@nvidia.com\nCc: stable@dpdk.org\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rxq.c | 8 +++++---\n 1 file changed, 5 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 9220bb2c15c..4567b43c1b6 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -129,7 +129,7 @@ rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)\n * Pointer to RX queue structure.\n *\n * @return\n- * 0 on success, errno value on failure.\n+ * 0 on success, negative errno value on failure.\n */\n static int\n rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)\n@@ -220,7 +220,7 @@ rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)\n * Pointer to RX queue structure.\n *\n * @return\n- * 0 on success, errno value on failure.\n+ * 0 on success, negative errno value on failure.\n */\n int\n rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)\n@@ -233,7 +233,9 @@ rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)\n \t */\n \tif (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))\n \t\tret = rxq_alloc_elts_mprq(rxq_ctrl);\n-\treturn (ret || rxq_alloc_elts_sprq(rxq_ctrl));\n+\tif (ret == 0)\n+\t\tret = rxq_alloc_elts_sprq(rxq_ctrl);\n+\treturn ret;\n }\n \n /**\n", "prefixes": [ "v3", "05/14" ] }