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GET /api/patches/103069/?format=api
{ "id": 103069, "url": "http://patches.dpdk.org/api/patches/103069/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211027155055.32264-7-kai.ji@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211027155055.32264-7-kai.ji@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211027155055.32264-7-kai.ji@intel.com", "date": "2021-10-27T15:50:52", "name": "[v7,6/9] compress/qat: add gen specific implementation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ec15724f63fee11a10d6a99d43755989dd6ecb0c", "submitter": { "id": 2202, "url": "http://patches.dpdk.org/api/people/2202/?format=api", "name": "Ji, Kai", "email": "kai.ji@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211027155055.32264-7-kai.ji@intel.com/mbox/", "series": [ { "id": 20061, "url": "http://patches.dpdk.org/api/series/20061/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20061", "date": "2021-10-27T15:50:46", "name": "drivers/qat: isolate implementations of qat generations", "version": 7, "mbox": "http://patches.dpdk.org/series/20061/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103069/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/103069/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 334B9A0C47;\n\tWed, 27 Oct 2021 17:51:45 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 76756426DB;\n\tWed, 27 Oct 2021 17:51:17 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id AC2FF411FB\n for <dev@dpdk.org>; Wed, 27 Oct 2021 17:51:10 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 Oct 2021 08:51:10 -0700", "from silpixa00400272.ir.intel.com (HELO\n silpixa00400272.ger.corp.intel.com) ([10.237.223.111])\n by orsmga001.jf.intel.com with ESMTP; 27 Oct 2021 08:51:08 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10150\"; a=\"217101402\"", "E=Sophos;i=\"5.87,187,1631602800\"; d=\"scan'208\";a=\"217101402\"", "E=Sophos;i=\"5.87,187,1631602800\"; d=\"scan'208\";a=\"529672590\"" ], "X-ExtLoop1": "1", "From": "Kai Ji <kai.ji@intel.com>", "To": "dev@dpdk.org", "Cc": "Fan Zhang <roy.fan.zhang@intel.com>,\n Adam Dybkowski <adamx.dybkowski@intel.com>,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>, Kai Ji <kai.ji@intel.com>", "Date": "Wed, 27 Oct 2021 16:50:52 +0100", "Message-Id": "<20211027155055.32264-7-kai.ji@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211027155055.32264-1-kai.ji@intel.com>", "References": "<20211026171633.19498-1-kai.ji@intel.com>\n <20211027155055.32264-1-kai.ji@intel.com>", "Subject": "[dpdk-dev] [dpdk-dev v7 6/9] compress/qat: add gen specific\n implementation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Fan Zhang <roy.fan.zhang@intel.com>\n\nThis patch replaces the mixed QAT compression support\nimplementation by separate files with shared or individual\nimplementation for specific QAT generation.\n\nSigned-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\nSigned-off-by: Fan Zhang <roy.fan.zhang@intel.com>\nSigned-off-by: Kai Ji <kai.ji@intel.com>\nAcked-by: Ciara Power <ciara.power@intel.com>\n---\n drivers/common/qat/meson.build | 4 +-\n drivers/compress/qat/dev/qat_comp_pmd_gen1.c | 176 +++++++++++++++\n drivers/compress/qat/dev/qat_comp_pmd_gen2.c | 30 +++\n drivers/compress/qat/dev/qat_comp_pmd_gen3.c | 30 +++\n drivers/compress/qat/dev/qat_comp_pmd_gen4.c | 213 +++++++++++++++++++\n drivers/compress/qat/dev/qat_comp_pmd_gens.h | 30 +++\n 6 files changed, 482 insertions(+), 1 deletion(-)\n create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen1.c\n create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen2.c\n create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen3.c\n create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen4.c\n create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gens.h\n\n--\n2.17.1", "diff": "diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build\nindex 532e0fabb3..8a1c6d64e8 100644\n--- a/drivers/common/qat/meson.build\n+++ b/drivers/common/qat/meson.build\n@@ -62,7 +62,9 @@ includes += include_directories(\n )\n\n if qat_compress\n- foreach f: ['qat_comp_pmd.c', 'qat_comp.c']\n+ foreach f: ['qat_comp_pmd.c', 'qat_comp.c',\n+ 'dev/qat_comp_pmd_gen1.c', 'dev/qat_comp_pmd_gen2.c',\n+ 'dev/qat_comp_pmd_gen3.c', 'dev/qat_comp_pmd_gen4.c']\n sources += files(join_paths(qat_compress_relpath, f))\n endforeach\n endif\ndiff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen1.c b/drivers/compress/qat/dev/qat_comp_pmd_gen1.c\nnew file mode 100644\nindex 0000000000..e3e75c8289\n--- /dev/null\n+++ b/drivers/compress/qat/dev/qat_comp_pmd_gen1.c\n@@ -0,0 +1,176 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#include <rte_compressdev.h>\n+#include <rte_compressdev_pmd.h>\n+\n+#include \"qat_comp_pmd.h\"\n+#include \"qat_comp.h\"\n+#include \"qat_comp_pmd_gens.h\"\n+\n+#define QAT_NUM_INTERM_BUFS_GEN1 12\n+\n+const struct rte_compressdev_capabilities qat_gen1_comp_capabilities[] = {\n+\t{/* COMPRESSION - deflate */\n+\t .algo = RTE_COMP_ALGO_DEFLATE,\n+\t .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |\n+\t\t\t\tRTE_COMP_FF_CRC32_CHECKSUM |\n+\t\t\t\tRTE_COMP_FF_ADLER32_CHECKSUM |\n+\t\t\t\tRTE_COMP_FF_CRC32_ADLER32_CHECKSUM |\n+\t\t\t\tRTE_COMP_FF_SHAREABLE_PRIV_XFORM |\n+\t\t\t\tRTE_COMP_FF_HUFFMAN_FIXED |\n+\t\t\t\tRTE_COMP_FF_HUFFMAN_DYNAMIC |\n+\t\t\t\tRTE_COMP_FF_OOP_SGL_IN_SGL_OUT |\n+\t\t\t\tRTE_COMP_FF_OOP_SGL_IN_LB_OUT |\n+\t\t\t\tRTE_COMP_FF_OOP_LB_IN_SGL_OUT |\n+\t\t\t\tRTE_COMP_FF_STATEFUL_DECOMPRESSION,\n+\t .window_size = {.min = 15, .max = 15, .increment = 0} },\n+\t{RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };\n+\n+static int\n+qat_comp_dev_config_gen1(struct rte_compressdev *dev,\n+\t\tstruct rte_compressdev_config *config)\n+{\n+\tstruct qat_comp_dev_private *comp_dev = dev->data->dev_private;\n+\n+\tif (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {\n+\t\tQAT_LOG(WARNING,\n+\t\t\t\"RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so\"\n+\t\t\t\"QAT device can't be used for Dynamic Deflate.\");\n+\t} else {\n+\t\tcomp_dev->interm_buff_mz =\n+\t\t\t\tqat_comp_setup_inter_buffers(comp_dev,\n+\t\t\t\t\tRTE_PMD_QAT_COMP_IM_BUFFER_SIZE);\n+\t\tif (comp_dev->interm_buff_mz == NULL)\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn qat_comp_dev_config(dev, config);\n+}\n+\n+struct rte_compressdev_ops qat_comp_ops_gen1 = {\n+\n+\t/* Device related operations */\n+\t.dev_configure\t\t= qat_comp_dev_config_gen1,\n+\t.dev_start\t\t= qat_comp_dev_start,\n+\t.dev_stop\t\t= qat_comp_dev_stop,\n+\t.dev_close\t\t= qat_comp_dev_close,\n+\t.dev_infos_get\t\t= qat_comp_dev_info_get,\n+\n+\t.stats_get\t\t= qat_comp_stats_get,\n+\t.stats_reset\t\t= qat_comp_stats_reset,\n+\t.queue_pair_setup\t= qat_comp_qp_setup,\n+\t.queue_pair_release\t= qat_comp_qp_release,\n+\n+\t/* Compression related operations */\n+\t.private_xform_create\t= qat_comp_private_xform_create,\n+\t.private_xform_free\t= qat_comp_private_xform_free,\n+\t.stream_create\t\t= qat_comp_stream_create,\n+\t.stream_free\t\t= qat_comp_stream_free\n+};\n+\n+struct qat_comp_capabilities_info\n+qat_comp_cap_get_gen1(struct qat_pci_device *qat_dev __rte_unused)\n+{\n+\tstruct qat_comp_capabilities_info capa_info = {\n+\t\t.data = qat_gen1_comp_capabilities,\n+\t\t.size = sizeof(qat_gen1_comp_capabilities)\n+\t};\n+\treturn capa_info;\n+}\n+\n+uint16_t\n+qat_comp_get_ram_bank_flags_gen1(void)\n+{\n+\t/* Enable A, B, C, D, and E (CAMs). */\n+\treturn ICP_QAT_FW_COMP_RAM_FLAGS_BUILD(\n+\t\t\tICP_QAT_FW_COMP_BANK_DISABLED, /* Bank I */\n+\t\t\tICP_QAT_FW_COMP_BANK_DISABLED, /* Bank H */\n+\t\t\tICP_QAT_FW_COMP_BANK_DISABLED, /* Bank G */\n+\t\t\tICP_QAT_FW_COMP_BANK_DISABLED, /* Bank F */\n+\t\t\tICP_QAT_FW_COMP_BANK_ENABLED, /* Bank E */\n+\t\t\tICP_QAT_FW_COMP_BANK_ENABLED, /* Bank D */\n+\t\t\tICP_QAT_FW_COMP_BANK_ENABLED, /* Bank C */\n+\t\t\tICP_QAT_FW_COMP_BANK_ENABLED, /* Bank B */\n+\t\t\tICP_QAT_FW_COMP_BANK_ENABLED); /* Bank A */\n+}\n+\n+int\n+qat_comp_set_slice_cfg_word_gen1(struct qat_comp_xform *qat_xform,\n+\t\tconst struct rte_comp_xform *xform,\n+\t\t__rte_unused enum rte_comp_op_type op_type,\n+\t\tuint32_t *comp_slice_cfg_word)\n+{\n+\tunsigned int algo, comp_level, direction;\n+\n+\tif (xform->compress.algo == RTE_COMP_ALGO_DEFLATE)\n+\t\talgo = ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE;\n+\telse {\n+\t\tQAT_LOG(ERR, \"compression algorithm not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {\n+\t\tdirection = ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS;\n+\t\tcomp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;\n+\t} else {\n+\t\tdirection = ICP_QAT_HW_COMPRESSION_DIR_COMPRESS;\n+\n+\t\tif (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)\n+\t\t\tcomp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;\n+\t\telse if (xform->compress.level == 1)\n+\t\t\tcomp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;\n+\t\telse if (xform->compress.level == 2)\n+\t\t\tcomp_level = ICP_QAT_HW_COMPRESSION_DEPTH_4;\n+\t\telse if (xform->compress.level == 3)\n+\t\t\tcomp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;\n+\t\telse if (xform->compress.level >= 4 &&\n+\t\t\t xform->compress.level <= 9)\n+\t\t\tcomp_level = ICP_QAT_HW_COMPRESSION_DEPTH_16;\n+\t\telse {\n+\t\t\tQAT_LOG(ERR, \"compression level not supported\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tcomp_slice_cfg_word[0] =\n+\t\t\tICP_QAT_HW_COMPRESSION_CONFIG_BUILD(\n+\t\t\t\tdirection,\n+\t\t\t\t/* In CPM 1.6 only valid mode ! */\n+\t\t\t\tICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED,\n+\t\t\t\talgo,\n+\t\t\t\t/* Translate level to depth */\n+\t\t\t\tcomp_level,\n+\t\t\t\tICP_QAT_HW_COMPRESSION_FILE_TYPE_0);\n+\n+\treturn 0;\n+}\n+\n+static unsigned int\n+qat_comp_get_num_im_bufs_required_gen1(void)\n+{\n+\treturn QAT_NUM_INTERM_BUFS_GEN1;\n+}\n+\n+uint64_t\n+qat_comp_get_features_gen1(void)\n+{\n+\treturn RTE_COMPDEV_FF_HW_ACCELERATED;\n+}\n+\n+RTE_INIT(qat_comp_pmd_gen1_init)\n+{\n+\tqat_comp_gen_dev_ops[QAT_GEN1].compressdev_ops =\n+\t\t\t&qat_comp_ops_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN1].qat_comp_get_capabilities =\n+\t\t\tqat_comp_cap_get_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN1].qat_comp_get_num_im_bufs_required =\n+\t\t\tqat_comp_get_num_im_bufs_required_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN1].qat_comp_get_ram_bank_flags =\n+\t\t\tqat_comp_get_ram_bank_flags_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN1].qat_comp_set_slice_cfg_word =\n+\t\t\tqat_comp_set_slice_cfg_word_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN1].qat_comp_get_feature_flags =\n+\t\t\tqat_comp_get_features_gen1;\n+}\ndiff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen2.c b/drivers/compress/qat/dev/qat_comp_pmd_gen2.c\nnew file mode 100644\nindex 0000000000..fd6c966f26\n--- /dev/null\n+++ b/drivers/compress/qat/dev/qat_comp_pmd_gen2.c\n@@ -0,0 +1,30 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#include \"qat_comp_pmd.h\"\n+#include \"qat_comp_pmd_gens.h\"\n+\n+#define QAT_NUM_INTERM_BUFS_GEN2 20\n+\n+static unsigned int\n+qat_comp_get_num_im_bufs_required_gen2(void)\n+{\n+\treturn QAT_NUM_INTERM_BUFS_GEN2;\n+}\n+\n+RTE_INIT(qat_comp_pmd_gen2_init)\n+{\n+\tqat_comp_gen_dev_ops[QAT_GEN2].compressdev_ops =\n+\t\t\t&qat_comp_ops_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN2].qat_comp_get_capabilities =\n+\t\t\tqat_comp_cap_get_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN2].qat_comp_get_num_im_bufs_required =\n+\t\t\tqat_comp_get_num_im_bufs_required_gen2;\n+\tqat_comp_gen_dev_ops[QAT_GEN2].qat_comp_get_ram_bank_flags =\n+\t\t\tqat_comp_get_ram_bank_flags_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN2].qat_comp_set_slice_cfg_word =\n+\t\t\tqat_comp_set_slice_cfg_word_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN2].qat_comp_get_feature_flags =\n+\t\t\tqat_comp_get_features_gen1;\n+}\ndiff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen3.c b/drivers/compress/qat/dev/qat_comp_pmd_gen3.c\nnew file mode 100644\nindex 0000000000..fccb0941f1\n--- /dev/null\n+++ b/drivers/compress/qat/dev/qat_comp_pmd_gen3.c\n@@ -0,0 +1,30 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#include \"qat_comp_pmd.h\"\n+#include \"qat_comp_pmd_gens.h\"\n+\n+#define QAT_NUM_INTERM_BUFS_GEN3 64\n+\n+static unsigned int\n+qat_comp_get_num_im_bufs_required_gen3(void)\n+{\n+\treturn QAT_NUM_INTERM_BUFS_GEN3;\n+}\n+\n+RTE_INIT(qat_comp_pmd_gen3_init)\n+{\n+\tqat_comp_gen_dev_ops[QAT_GEN3].compressdev_ops =\n+\t\t\t&qat_comp_ops_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN3].qat_comp_get_capabilities =\n+\t\t\tqat_comp_cap_get_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN3].qat_comp_get_num_im_bufs_required =\n+\t\t\tqat_comp_get_num_im_bufs_required_gen3;\n+\tqat_comp_gen_dev_ops[QAT_GEN3].qat_comp_get_ram_bank_flags =\n+\t\t\tqat_comp_get_ram_bank_flags_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN3].qat_comp_set_slice_cfg_word =\n+\t\t\tqat_comp_set_slice_cfg_word_gen1;\n+\tqat_comp_gen_dev_ops[QAT_GEN3].qat_comp_get_feature_flags =\n+\t\t\tqat_comp_get_features_gen1;\n+}\ndiff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c\nnew file mode 100644\nindex 0000000000..79b2ceb414\n--- /dev/null\n+++ b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c\n@@ -0,0 +1,213 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#include \"qat_comp.h\"\n+#include \"qat_comp_pmd.h\"\n+#include \"qat_comp_pmd_gens.h\"\n+#include \"icp_qat_hw_gen4_comp.h\"\n+#include \"icp_qat_hw_gen4_comp_defs.h\"\n+\n+#define QAT_NUM_INTERM_BUFS_GEN4 0\n+\n+static const struct rte_compressdev_capabilities\n+qat_gen4_comp_capabilities[] = {\n+\t{/* COMPRESSION - deflate */\n+\t .algo = RTE_COMP_ALGO_DEFLATE,\n+\t .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |\n+\t\t\t\tRTE_COMP_FF_CRC32_CHECKSUM |\n+\t\t\t\tRTE_COMP_FF_ADLER32_CHECKSUM |\n+\t\t\t\tRTE_COMP_FF_CRC32_ADLER32_CHECKSUM |\n+\t\t\t\tRTE_COMP_FF_SHAREABLE_PRIV_XFORM |\n+\t\t\t\tRTE_COMP_FF_HUFFMAN_FIXED |\n+\t\t\t\tRTE_COMP_FF_HUFFMAN_DYNAMIC |\n+\t\t\t\tRTE_COMP_FF_OOP_SGL_IN_SGL_OUT |\n+\t\t\t\tRTE_COMP_FF_OOP_SGL_IN_LB_OUT |\n+\t\t\t\tRTE_COMP_FF_OOP_LB_IN_SGL_OUT,\n+\t .window_size = {.min = 15, .max = 15, .increment = 0} },\n+\t{RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };\n+\n+static int\n+qat_comp_dev_config_gen4(struct rte_compressdev *dev,\n+\t\tstruct rte_compressdev_config *config)\n+{\n+\t/* QAT GEN4 doesn't need preallocated intermediate buffers */\n+\n+\treturn qat_comp_dev_config(dev, config);\n+}\n+\n+static struct rte_compressdev_ops qat_comp_ops_gen4 = {\n+\n+\t/* Device related operations */\n+\t.dev_configure\t\t= qat_comp_dev_config_gen4,\n+\t.dev_start\t\t= qat_comp_dev_start,\n+\t.dev_stop\t\t= qat_comp_dev_stop,\n+\t.dev_close\t\t= qat_comp_dev_close,\n+\t.dev_infos_get\t\t= qat_comp_dev_info_get,\n+\n+\t.stats_get\t\t= qat_comp_stats_get,\n+\t.stats_reset\t\t= qat_comp_stats_reset,\n+\t.queue_pair_setup\t= qat_comp_qp_setup,\n+\t.queue_pair_release\t= qat_comp_qp_release,\n+\n+\t/* Compression related operations */\n+\t.private_xform_create\t= qat_comp_private_xform_create,\n+\t.private_xform_free\t= qat_comp_private_xform_free,\n+\t.stream_create\t\t= qat_comp_stream_create,\n+\t.stream_free\t\t= qat_comp_stream_free\n+};\n+\n+static struct qat_comp_capabilities_info\n+qat_comp_cap_get_gen4(struct qat_pci_device *qat_dev __rte_unused)\n+{\n+\tstruct qat_comp_capabilities_info capa_info = {\n+\t\t.data = qat_gen4_comp_capabilities,\n+\t\t.size = sizeof(qat_gen4_comp_capabilities)\n+\t};\n+\treturn capa_info;\n+}\n+\n+static uint16_t\n+qat_comp_get_ram_bank_flags_gen4(void)\n+{\n+\treturn 0;\n+}\n+\n+static int\n+qat_comp_set_slice_cfg_word_gen4(struct qat_comp_xform *qat_xform,\n+\t\tconst struct rte_comp_xform *xform,\n+\t\tenum rte_comp_op_type op_type, uint32_t *comp_slice_cfg_word)\n+{\n+\tif (qat_xform->qat_comp_request_type ==\n+\t\t\tQAT_COMP_REQUEST_FIXED_COMP_STATELESS ||\n+\t qat_xform->qat_comp_request_type ==\n+\t\t\tQAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {\n+\t\t/* Compression */\n+\t\tstruct icp_qat_hw_comp_20_config_csr_upper hw_comp_upper_csr;\n+\t\tstruct icp_qat_hw_comp_20_config_csr_lower hw_comp_lower_csr;\n+\n+\t\tmemset(&hw_comp_upper_csr, 0, sizeof(hw_comp_upper_csr));\n+\t\tmemset(&hw_comp_lower_csr, 0, sizeof(hw_comp_lower_csr));\n+\n+\t\thw_comp_lower_csr.lllbd =\n+\t\t\tICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_DISABLED;\n+\n+\t\tif (xform->compress.algo == RTE_COMP_ALGO_DEFLATE) {\n+\t\t\thw_comp_lower_csr.skip_ctrl =\n+\t\t\t\tICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL;\n+\n+\t\t\tif (qat_xform->qat_comp_request_type ==\n+\t\t\t\tQAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {\n+\t\t\t\thw_comp_lower_csr.algo =\n+\t\t\t\t\tICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77;\n+\t\t\t\thw_comp_lower_csr.lllbd =\n+\t\t\t\t ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED;\n+\t\t\t} else {\n+\t\t\t\thw_comp_lower_csr.algo =\n+\t\t\t\t ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE;\n+\t\t\t\thw_comp_upper_csr.scb_ctrl =\n+\t\t\t\t\tICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE;\n+\t\t\t}\n+\n+\t\t\tif (op_type == RTE_COMP_OP_STATEFUL) {\n+\t\t\t\thw_comp_upper_csr.som_ctrl =\n+\t\t\t\t ICP_QAT_HW_COMP_20_SOM_CONTROL_REPLAY_MODE;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tQAT_LOG(ERR, \"Compression algorithm not supported\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tswitch (xform->compress.level) {\n+\t\tcase 1:\n+\t\tcase 2:\n+\t\tcase 3:\n+\t\tcase 4:\n+\t\tcase 5:\n+\t\t\thw_comp_lower_csr.sd =\n+\t\t\t\t\tICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1;\n+\t\t\thw_comp_lower_csr.hash_col =\n+\t\t\t ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_DONT_ALLOW;\n+\t\t\tbreak;\n+\t\tcase 6:\n+\t\tcase 7:\n+\t\tcase 8:\n+\t\tcase RTE_COMP_LEVEL_PMD_DEFAULT:\n+\t\t\thw_comp_lower_csr.sd =\n+\t\t\t\t\tICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_6;\n+\t\t\tbreak;\n+\t\tcase 9:\n+\t\tcase 10:\n+\t\tcase 11:\n+\t\tcase 12:\n+\t\t\thw_comp_lower_csr.sd =\n+\t\t\t\t\tICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_9;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tQAT_LOG(ERR, \"Compression level not supported\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\thw_comp_lower_csr.abd = ICP_QAT_HW_COMP_20_ABD_ABD_DISABLED;\n+\t\thw_comp_lower_csr.hash_update =\n+\t\t\tICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW;\n+\t\thw_comp_lower_csr.edmm =\n+\t\t ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED;\n+\n+\t\thw_comp_upper_csr.nice =\n+\t\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL;\n+\t\thw_comp_upper_csr.lazy =\n+\t\t\tICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL;\n+\n+\t\tcomp_slice_cfg_word[0] =\n+\t\t\t\tICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(\n+\t\t\t\t\thw_comp_lower_csr);\n+\t\tcomp_slice_cfg_word[1] =\n+\t\t\t\tICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(\n+\t\t\t\t\thw_comp_upper_csr);\n+\t} else {\n+\t\t/* Decompression */\n+\t\tstruct icp_qat_hw_decomp_20_config_csr_lower\n+\t\t\t\thw_decomp_lower_csr;\n+\n+\t\tmemset(&hw_decomp_lower_csr, 0, sizeof(hw_decomp_lower_csr));\n+\n+\t\tif (xform->compress.algo == RTE_COMP_ALGO_DEFLATE)\n+\t\t\thw_decomp_lower_csr.algo =\n+\t\t\t\tICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE;\n+\t\telse {\n+\t\t\tQAT_LOG(ERR, \"Compression algorithm not supported\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tcomp_slice_cfg_word[0] =\n+\t\t\t\tICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(\n+\t\t\t\t\thw_decomp_lower_csr);\n+\t\tcomp_slice_cfg_word[1] = 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static unsigned int\n+qat_comp_get_num_im_bufs_required_gen4(void)\n+{\n+\treturn QAT_NUM_INTERM_BUFS_GEN4;\n+}\n+\n+\n+RTE_INIT(qat_comp_pmd_gen4_init)\n+{\n+\tqat_comp_gen_dev_ops[QAT_GEN4].compressdev_ops =\n+\t\t\t&qat_comp_ops_gen4;\n+\tqat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_capabilities =\n+\t\t\tqat_comp_cap_get_gen4;\n+\tqat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_num_im_bufs_required =\n+\t\t\tqat_comp_get_num_im_bufs_required_gen4;\n+\tqat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_ram_bank_flags =\n+\t\t\tqat_comp_get_ram_bank_flags_gen4;\n+\tqat_comp_gen_dev_ops[QAT_GEN4].qat_comp_set_slice_cfg_word =\n+\t\t\tqat_comp_set_slice_cfg_word_gen4;\n+\tqat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_feature_flags =\n+\t\t\tqat_comp_get_features_gen1;\n+}\ndiff --git a/drivers/compress/qat/dev/qat_comp_pmd_gens.h b/drivers/compress/qat/dev/qat_comp_pmd_gens.h\nnew file mode 100644\nindex 0000000000..67293092ea\n--- /dev/null\n+++ b/drivers/compress/qat/dev/qat_comp_pmd_gens.h\n@@ -0,0 +1,30 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#ifndef _QAT_COMP_PMD_GENS_H_\n+#define _QAT_COMP_PMD_GENS_H_\n+\n+#include <rte_compressdev.h>\n+#include <rte_compressdev_pmd.h>\n+#include <stdint.h>\n+\n+#include \"qat_comp_pmd.h\"\n+\n+extern const struct rte_compressdev_capabilities qat_gen1_comp_capabilities[];\n+\n+struct qat_comp_capabilities_info\n+qat_comp_cap_get_gen1(struct qat_pci_device *qat_dev);\n+\n+uint16_t qat_comp_get_ram_bank_flags_gen1(void);\n+\n+int qat_comp_set_slice_cfg_word_gen1(struct qat_comp_xform *qat_xform,\n+\t\tconst struct rte_comp_xform *xform,\n+\t\tenum rte_comp_op_type op_type,\n+\t\tuint32_t *comp_slice_cfg_word);\n+\n+uint64_t qat_comp_get_features_gen1(void);\n+\n+extern struct rte_compressdev_ops qat_comp_ops_gen1;\n+\n+#endif /* _QAT_COMP_PMD_GENS_H_ */\n", "prefixes": [ "v7", "6/9" ] }