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GET /api/patches/103066/?format=api
{ "id": 103066, "url": "http://patches.dpdk.org/api/patches/103066/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211027155055.32264-4-kai.ji@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211027155055.32264-4-kai.ji@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211027155055.32264-4-kai.ji@intel.com", "date": "2021-10-27T15:50:49", "name": "[v7,3/9] common/qat: add gen specific queue pair function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3ae5ac5d6fce6bf0c8d3624cd47dc8bd82efb98b", "submitter": { "id": 2202, "url": "http://patches.dpdk.org/api/people/2202/?format=api", "name": "Ji, Kai", "email": "kai.ji@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211027155055.32264-4-kai.ji@intel.com/mbox/", "series": [ { "id": 20061, "url": "http://patches.dpdk.org/api/series/20061/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20061", "date": "2021-10-27T15:50:46", "name": "drivers/qat: isolate implementations of qat generations", "version": 7, "mbox": "http://patches.dpdk.org/series/20061/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103066/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/103066/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C017AA0C47;\n\tWed, 27 Oct 2021 17:51:21 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 66E2441C3B;\n\tWed, 27 Oct 2021 17:51:11 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id 28353411FE\n for <dev@dpdk.org>; Wed, 27 Oct 2021 17:51:05 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 Oct 2021 08:51:04 -0700", "from silpixa00400272.ir.intel.com (HELO\n silpixa00400272.ger.corp.intel.com) ([10.237.223.111])\n by orsmga001.jf.intel.com with ESMTP; 27 Oct 2021 08:51:03 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10150\"; a=\"217101370\"", "E=Sophos;i=\"5.87,187,1631602800\"; d=\"scan'208\";a=\"217101370\"", "E=Sophos;i=\"5.87,187,1631602800\"; d=\"scan'208\";a=\"529672544\"" ], "X-ExtLoop1": "1", "From": "Kai Ji <kai.ji@intel.com>", "To": "dev@dpdk.org", "Cc": "Fan Zhang <roy.fan.zhang@intel.com>", "Date": "Wed, 27 Oct 2021 16:50:49 +0100", "Message-Id": "<20211027155055.32264-4-kai.ji@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211027155055.32264-1-kai.ji@intel.com>", "References": "<20211026171633.19498-1-kai.ji@intel.com>\n <20211027155055.32264-1-kai.ji@intel.com>", "Subject": "[dpdk-dev] [dpdk-dev v7 3/9] common/qat: add gen specific queue\n pair function", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Fan Zhang <roy.fan.zhang@intel.com>\n\nThis patch adds the queue pair data structure and function\nprototypes for different QAT generations.\n\nSigned-off-by: Fan Zhang <roy.fan.zhang@intel.com>\nAcked-by: Ciara Power <ciara.power@intel.com>\n---\n drivers/common/qat/qat_qp.c | 3 ++\n drivers/common/qat/qat_qp.h | 103 ++++++++++++++++++++++++------------\n 2 files changed, 71 insertions(+), 35 deletions(-)\n\n--\n2.17.1", "diff": "diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c\nindex b8c6000e86..27994036b8 100644\n--- a/drivers/common/qat/qat_qp.c\n+++ b/drivers/common/qat/qat_qp.c\n@@ -34,6 +34,9 @@\n \tADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \\\n \t(ADF_ARB_REG_SLOT * index), value)\n\n+struct qat_qp_hw_spec_funcs*\n+\tqat_qp_hw_spec[QAT_N_GENS];\n+\n __extension__\n const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]\n \t\t\t\t\t [ADF_MAX_QPS_ON_ANY_SERVICE] = {\ndiff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h\nindex e1627197fa..726cd2ef61 100644\n--- a/drivers/common/qat/qat_qp.h\n+++ b/drivers/common/qat/qat_qp.h\n@@ -7,8 +7,6 @@\n #include \"qat_common.h\"\n #include \"adf_transport_access_macros.h\"\n\n-struct qat_pci_device;\n-\n #define QAT_CSR_HEAD_WRITE_THRESH 32U\n /* number of requests to accumulate before writing head CSR */\n\n@@ -24,37 +22,7 @@ struct qat_pci_device;\n #define QAT_GEN4_BUNDLE_NUM 4\n #define QAT_GEN4_QPS_PER_BUNDLE_NUM 1\n\n-/**\n- * Structure with data needed for creation of queue pair.\n- */\n-struct qat_qp_hw_data {\n-\tenum qat_service_type service_type;\n-\tuint8_t hw_bundle_num;\n-\tuint8_t tx_ring_num;\n-\tuint8_t rx_ring_num;\n-\tuint16_t tx_msg_size;\n-\tuint16_t rx_msg_size;\n-};\n-\n-/**\n- * Structure with data needed for creation of queue pair on gen4.\n- */\n-struct qat_qp_gen4_data {\n-\tstruct qat_qp_hw_data qat_qp_hw_data;\n-\tuint8_t reserved;\n-\tuint8_t valid;\n-};\n-\n-/**\n- * Structure with data needed for creation of queue pair.\n- */\n-struct qat_qp_config {\n-\tconst struct qat_qp_hw_data *hw;\n-\tuint32_t nb_descriptors;\n-\tuint32_t cookie_size;\n-\tint socket_id;\n-\tconst char *service_str;\n-};\n+struct qat_pci_device;\n\n /**\n * Structure associated with each queue.\n@@ -96,8 +64,28 @@ struct qat_qp {\n \tuint16_t min_enq_burst_threshold;\n } __rte_cache_aligned;\n\n-extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];\n-extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];\n+/**\n+ * Structure with data needed for creation of queue pair.\n+ */\n+struct qat_qp_hw_data {\n+\tenum qat_service_type service_type;\n+\tuint8_t hw_bundle_num;\n+\tuint8_t tx_ring_num;\n+\tuint8_t rx_ring_num;\n+\tuint16_t tx_msg_size;\n+\tuint16_t rx_msg_size;\n+};\n+\n+/**\n+ * Structure with data needed for creation of queue pair.\n+ */\n+struct qat_qp_config {\n+\tconst struct qat_qp_hw_data *hw;\n+\tuint32_t nb_descriptors;\n+\tuint32_t cookie_size;\n+\tint socket_id;\n+\tconst char *service_str;\n+};\n\n uint16_t\n qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);\n@@ -136,4 +124,49 @@ qat_select_valid_queue(struct qat_pci_device *qat_dev, int qp_id,\n int\n qat_read_qp_config(struct qat_pci_device *qat_dev);\n\n+/**\n+ * Function prototypes for GENx specific queue pair operations.\n+ **/\n+typedef int (*qat_qp_rings_per_service_t)\n+\t\t(struct qat_pci_device *, enum qat_service_type);\n+\n+typedef void (*qat_qp_build_ring_base_t)(void *, struct qat_queue *);\n+\n+typedef void (*qat_qp_adf_arb_enable_t)(const struct qat_queue *, void *,\n+\t\trte_spinlock_t *);\n+\n+typedef void (*qat_qp_adf_arb_disable_t)(const struct qat_queue *, void *,\n+\t\trte_spinlock_t *);\n+\n+typedef void (*qat_qp_adf_configure_queues_t)(struct qat_qp *);\n+\n+typedef void (*qat_qp_csr_write_tail_t)(struct qat_qp *qp, struct qat_queue *q);\n+\n+typedef void (*qat_qp_csr_write_head_t)(struct qat_qp *qp, struct qat_queue *q,\n+\t\tuint32_t new_head);\n+\n+typedef void (*qat_qp_csr_setup_t)(struct qat_pci_device*, void *,\n+\t\tstruct qat_qp *);\n+\n+typedef const struct qat_qp_hw_data * (*qat_qp_get_hw_data_t)(\n+\t\tstruct qat_pci_device *dev, enum qat_service_type service_type,\n+\t\tuint16_t qp_id);\n+\n+struct qat_qp_hw_spec_funcs {\n+\tqat_qp_rings_per_service_t\tqat_qp_rings_per_service;\n+\tqat_qp_build_ring_base_t\tqat_qp_build_ring_base;\n+\tqat_qp_adf_arb_enable_t\t\tqat_qp_adf_arb_enable;\n+\tqat_qp_adf_arb_disable_t\tqat_qp_adf_arb_disable;\n+\tqat_qp_adf_configure_queues_t\tqat_qp_adf_configure_queues;\n+\tqat_qp_csr_write_tail_t\t\tqat_qp_csr_write_tail;\n+\tqat_qp_csr_write_head_t\t\tqat_qp_csr_write_head;\n+\tqat_qp_csr_setup_t\t\tqat_qp_csr_setup;\n+\tqat_qp_get_hw_data_t\t\tqat_qp_get_hw_data;\n+};\n+\n+extern struct qat_qp_hw_spec_funcs *qat_qp_hw_spec[];\n+\n+extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];\n+extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];\n+\n #endif /* _QAT_QP_H_ */\n", "prefixes": [ "v7", "3/9" ] }