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GET /api/patches/102673/?format=api
{ "id": 102673, "url": "http://patches.dpdk.org/api/patches/102673/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211022154600.2180938-3-fkelly@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211022154600.2180938-3-fkelly@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211022154600.2180938-3-fkelly@nvidia.com", "date": "2021-10-22T15:45:53", "name": "[03/10] common/mlx5: update regex DevX commands", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "003f3f9360c9bc1426398b924e4fd9cc87b504ec", "submitter": { "id": 2387, "url": "http://patches.dpdk.org/api/people/2387/?format=api", "name": "Francis Kelly", "email": "fkelly@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211022154600.2180938-3-fkelly@nvidia.com/mbox/", "series": [ { "id": 19921, "url": "http://patches.dpdk.org/api/series/19921/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19921", "date": "2021-10-22T15:45:51", "name": "[01/10] common/mlx5: update PRM definitions for regex availability", "version": 1, "mbox": "http://patches.dpdk.org/series/19921/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/102673/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/102673/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4BB51A0C43;\n\tFri, 22 Oct 2021 17:48:03 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2BE73411EA;\n\tFri, 22 Oct 2021 17:48:03 +0200 (CEST)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2084.outbound.protection.outlook.com [40.107.94.84])\n by mails.dpdk.org (Postfix) with ESMTP id EE79A41149\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Francis Kelly <fkelly@nvidia.com>", "To": "<tmonjalon@nvidia.com>, Matan Azrad <matan@nvidia.com>, \"Viacheslav\n Ovsiienko\" <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>", "CC": "<jamhunter@nvidia.com>, <aagbarih@nvidia.com>, <dev@dpdk.org>, Ady Agbarih\n <adypodoman@gmail.com>", "Date": "Fri, 22 Oct 2021 15:45:53 +0000", "Message-ID": "<20211022154600.2180938-3-fkelly@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211022154600.2180938-1-fkelly@nvidia.com>", "References": "<20211022154600.2180938-1-fkelly@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "709f5adc-06a0-4dfa-55aa-08d995734ec5", "X-MS-TrafficTypeDiagnostic": "BYAPR12MB3128:", "X-Microsoft-Antispam-PRVS": "\n <BYAPR12MB31285814BFC10ED348546165B9809@BYAPR12MB3128.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:5236;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n KUmGs1+jK3kJczB/L3SlwOLK/XRz5qEOIKMRRL9exW/zrjUEq6MNFp5nrVDkHmzZY1dOer5Fughw3UOg6/9BkxGKb7H+1nfK0KUK0wt4OwENYjCkNaPSYFiwBSn7rhK+o7EJXYvIIRHWeZASfZtr9Gh9XT24eyT3/DR5xVObM19t3fqSTzh7vX9i69zomH604fFQZah7A+pyxd8Xlcf0ke9g5vIEAnXLkMIOra7wj7t8jb3rgf/iyo55+R5shSma57YF8ll1GLmz9MqyPqgBly3JbJhKe2updLk7YgRdMBX4QiOVTMe94lqYN+Sjjn95tSIB1XL3ni0kShbGCQBmplIcAD+Tmj1LuSz7z+ByXsvRP4XOdJudDVhcZ2Sqmrj3t1y5+0Pzu0Ok1vKTF+gENbKtO7s2KcDyh13nrlHuddkOF1oCWNKrsisU+O1Lee0Q4l+Cu23YWIels1IAwJXMkIDLujDUUrGVY+I4n99OWsIvhuxeAr5nWMUfXBGhmlppRh3T35XGHH6XOPePVcrHi+EC5yoZea0h0EZaHMVeRAdymmh0EpB/wcYXKfkugNIBL6XCV3qIEXIq5jZB66IJNpz6jZed+38mZHziyyhiY+CejzMOIOe21nlHq9Uk1gT3WjNYBxITtDJ1W8pE5Xapyg7636w0d5hNFVJuEyEyIeWlUUGglGO5ChLadiVB3ZiDPEOPR9+PTiVl4Lvi7e75jQ==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(36906005)(36860700001)(110136005)(316002)(1076003)(54906003)(2906002)(2616005)(70586007)(186003)(5660300002)(70206006)(6286002)(55016002)(36756003)(6666004)(7636003)(6636002)(26005)(16526019)(8936002)(336012)(83380400001)(47076005)(82310400003)(426003)(356005)(7696005)(86362001)(4326008)(508600001)(8676002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 Oct 2021 15:47:52.3669 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 709f5adc-06a0-4dfa-55aa-08d995734ec5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT014.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR12MB3128", "Subject": "[dpdk-dev] [PATCH 03/10] common/mlx5: update regex DevX commands", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ady Agbarih <adypodoman@gmail.com>\n\nThis patch modifies the SET_REGEXP_PARAMS devx command as follows:\n Remove DB setup devx command. The command is no longer needed\n in DPDK, it will always be invoked by the regex-daemon.\n Add new devx command, for programming rof rules for a specific\n engine. The command takes as an input an mkey of the rof.\n It also introduces a new field_select bit.\n\nSigned-off-by: Ady Agbarih <adypodoman@gmail.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 13 ++++++++-----\n drivers/regex/mlx5/mlx5_regex.c | 9 +++------\n drivers/regex/mlx5/mlx5_regex.h | 4 ++--\n drivers/regex/mlx5/mlx5_regex_devx.c | 15 ++++++++-------\n drivers/regex/mlx5/mlx5_rxp.c | 27 ---------------------------\n 5 files changed, 21 insertions(+), 47 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 8b0f2f1a89..fb75f2da4d 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3710,17 +3710,20 @@ struct mlx5_ifc_parse_graph_flex_out_bits {\n };\n \n struct regexp_params_field_select_bits {\n-\tu8 reserved_at_0[0x1e];\n+\tu8 reserved_at_0[0x1d];\n+\tu8 rof_mkey[0x1];\n \tu8 stop_engine[0x1];\n-\tu8 db_umem_id[0x1];\n+\tu8 reserved_at_1f[0x1];\n };\n \n struct mlx5_ifc_regexp_params_bits {\n \tu8 reserved_at_0[0x1f];\n \tu8 stop_engine[0x1];\n-\tu8 db_umem_id[0x20];\n-\tu8 db_umem_offset[0x40];\n-\tu8 reserved_at_80[0x100];\n+\tu8 reserved_at_20[0x60];\n+\tu8 rof_mkey[0x20];\n+\tu8 rof_size[0x20];\n+\tu8 rof_mkey_va[0x40];\n+\tu8 reserved_at_100[0x80];\n };\n \n struct mlx5_ifc_set_regexp_params_in_bits {\ndiff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex b7175ff8e9..4be36e40c5 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -55,12 +55,9 @@ mlx5_regex_stop(struct rte_regexdev *dev __rte_unused)\n \trte_free(priv->qps);\n \tpriv->qps = NULL;\n \n-\tfor (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {\n-\t\tif (priv->db[i].umem.umem)\n-\t\t\tmlx5_glue->devx_umem_dereg(priv->db[i].umem.umem);\n-\t\trte_free(priv->db[i].ptr);\n-\t\tpriv->db[i].ptr = NULL;\n-\t}\n+\tfor (i = 0; i < priv->nb_engines; i++)\n+\t\t/* Stop engine. */\n+\t\tmlx5_devx_regex_database_stop(priv->ctx, i);\n \n \treturn 0;\n }\ndiff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex 329768980d..c9586ae714 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -119,8 +119,8 @@ int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,\n \t\t\t\t uint32_t addr, uint32_t *data);\n int mlx5_devx_regex_database_stop(void *ctx, uint8_t engine);\n int mlx5_devx_regex_database_resume(void *ctx, uint8_t engine);\n-int mlx5_devx_regex_database_program(void *ctx, uint8_t engine,\n-\t\t\t\t uint32_t umem_id, uint64_t umem_offset);\n+int mlx5_devx_regex_rules_program(void *ctx, uint8_t engine, uint32_t rof_mkey,\n+\t\t\t\tuint32_t rof_size, uint64_t db_mkey_offset);\n \n /* mlx5_regex_control.c */\n int mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,\ndiff --git a/drivers/regex/mlx5/mlx5_regex_devx.c b/drivers/regex/mlx5/mlx5_regex_devx.c\nindex f66d7aa08b..d8515768c3 100644\n--- a/drivers/regex/mlx5/mlx5_regex_devx.c\n+++ b/drivers/regex/mlx5/mlx5_regex_devx.c\n@@ -103,8 +103,8 @@ mlx5_devx_regex_database_resume(void *ctx, uint8_t engine)\n }\n \n int\n-mlx5_devx_regex_database_program(void *ctx, uint8_t engine, uint32_t umem_id,\n-\t\t\t\t uint64_t umem_offset)\n+mlx5_devx_regex_rules_program(void *ctx, uint8_t engine, uint32_t rof_mkey,\n+\t\t\t\tuint32_t rof_size, uint64_t rof_mkey_va)\n {\n \tuint32_t out[MLX5_ST_SZ_DW(set_regexp_params_out)] = {0};\n \tuint32_t in[MLX5_ST_SZ_DW(set_regexp_params_in)] = {0};\n@@ -112,14 +112,15 @@ mlx5_devx_regex_database_program(void *ctx, uint8_t engine, uint32_t umem_id,\n \n \tMLX5_SET(set_regexp_params_in, in, opcode, MLX5_CMD_SET_REGEX_PARAMS);\n \tMLX5_SET(set_regexp_params_in, in, engine_id, engine);\n-\tMLX5_SET(set_regexp_params_in, in, regexp_params.db_umem_id, umem_id);\n-\tMLX5_SET64(set_regexp_params_in, in, regexp_params.db_umem_offset,\n-\t\t umem_offset);\n-\tMLX5_SET(set_regexp_params_in, in, field_select.db_umem_id, 1);\n+\tMLX5_SET(set_regexp_params_in, in, regexp_params.rof_mkey, rof_mkey);\n+\tMLX5_SET(set_regexp_params_in, in, regexp_params.rof_size, rof_size);\n+\tMLX5_SET64(set_regexp_params_in, in, regexp_params.rof_mkey_va,\n+\t\t rof_mkey_va);\n+\tMLX5_SET(set_regexp_params_in, in, field_select.rof_mkey, 1);\n \tret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,\n \t\t\t\t\t sizeof(out));\n \tif (ret) {\n-\t\tDRV_LOG(ERR, \"Database program failed %d\", ret);\n+\t\tDRV_LOG(ERR, \"Rules program failed %d\", ret);\n \t\trte_errno = errno;\n \t\treturn -errno;\n \t}\ndiff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c\nindex 5afdcb35cc..79f063a127 100644\n--- a/drivers/regex/mlx5/mlx5_rxp.c\n+++ b/drivers/regex/mlx5/mlx5_rxp.c\n@@ -33,8 +33,6 @@ rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,\n \t\t uint32_t address, uint32_t expected_value,\n \t\t uint32_t expected_mask, uint32_t timeout_ms, uint8_t id);\n static int\n-mlnx_set_database(struct mlx5_regex_priv *priv, uint8_t id, uint8_t db_to_use);\n-static int\n mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id);\n static int\n mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id);\n@@ -488,11 +486,6 @@ rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n \t\t}\n \n \t}\n-\tret = mlnx_set_database(priv, id, db_free);\n-\tif (ret < 0) {\n-\t\tDRV_LOG(ERR, \"Failed to register db memory!\");\n-\t\tgoto parse_error;\n-\t}\n \trte_free(tmp);\n \treturn 0;\n parse_error:\n@@ -500,26 +493,6 @@ rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n \treturn ret;\n }\n \n-static int\n-mlnx_set_database(struct mlx5_regex_priv *priv, uint8_t id, uint8_t db_to_use)\n-{\n-\tint ret;\n-\tuint32_t umem_id;\n-\n-\tret = mlx5_devx_regex_database_stop(priv->ctx, id);\n-\tif (ret < 0) {\n-\t\tDRV_LOG(ERR, \"stop engine failed!\");\n-\t\treturn ret;\n-\t}\n-\tumem_id = mlx5_os_get_umem_id(priv->db[db_to_use].umem.umem);\n-\tret = mlx5_devx_regex_database_program(priv->ctx, id, umem_id, 0);\n-\tif (ret < 0) {\n-\t\tDRV_LOG(ERR, \"program db failed!\");\n-\t\treturn ret;\n-\t}\n-\treturn 0;\n-}\n-\n static int\n mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id)\n {\n", "prefixes": [ "03/10" ] }