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GET /api/patches/102061/?format=api
{ "id": 102061, "url": "http://patches.dpdk.org/api/patches/102061/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211018144201.2028022-8-gakhil@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211018144201.2028022-8-gakhil@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211018144201.2028022-8-gakhil@marvell.com", "date": "2021-10-18T14:42:01", "name": "[v3,7/7] cryptodev: move device specific structures", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4e367e88326e7bfa927c5c332778f0585f057fe0", "submitter": { "id": 2094, "url": "http://patches.dpdk.org/api/people/2094/?format=api", "name": "Akhil Goyal", "email": "gakhil@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211018144201.2028022-8-gakhil@marvell.com/mbox/", "series": [ { "id": 19749, "url": "http://patches.dpdk.org/api/series/19749/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19749", "date": "2021-10-18T14:41:54", "name": "cryptodev: hide internal structures", "version": 3, "mbox": "http://patches.dpdk.org/series/19749/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/102061/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/102061/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A7594A0C43;\n\tMon, 18 Oct 2021 16:43:17 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 997E5410DA;\n\tMon, 18 Oct 2021 16:43:17 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 0A4F140142\n for <dev@dpdk.org>; Mon, 18 Oct 2021 16:43:15 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id\n 19ICjTHc025462;\n Mon, 18 Oct 2021 07:43:10 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 3bs1bujc5u-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 18 Oct 2021 07:43:10 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 18 Oct 2021 07:43:08 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 18 Oct 2021 07:43:08 -0700", "from localhost.localdomain (unknown [10.28.36.185])\n by maili.marvell.com (Postfix) with ESMTP id E28A85E6862;\n Mon, 18 Oct 2021 07:43:00 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=8vAve16fw618zjldlTPGwprb4fQZ2jBtYWgEaDI0Q2o=;\n b=cOogcgSiLY1CXbvHewt5PapRJVYqfDrXFQrulF8AnNx7I/1HX4CuEBLh8ewKBx41S2dH\n RgaPDLdeH8tI2WOchwtgvWEPS3nM5U5H+mJf5nHdXhYhbITdfsgMO5sek7uAMVCRUOf6\n 5jQy3jZcd7HaNLDVfB63mjoSOFRKYFccSaOswYlB4boDgEbqOZcUPVpMUjPhQhHLSmOJ\n aN8UEsYzrYu6QTLi1XMIVDxOwoflUPs83V4zwxnLCVA7IShmLESJ0oFjAJmTCg81c87P\n /qfrF5ODld+DklL2/FP0JiH5uqK25Fi1GzhnzkpajkUvR35xhivuMQEzPavyCx9sa1+G nA==", "From": "Akhil Goyal <gakhil@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>,\n <hemant.agrawal@nxp.com>, <anoobj@marvell.com>,\n <pablo.de.lara.guarch@intel.com>, <fiona.trahe@intel.com>,\n <declan.doherty@intel.com>, <matan@nvidia.com>, <g.singh@nxp.com>,\n <roy.fan.zhang@intel.com>, <jianjay.zhou@huawei.com>,\n <asomalap@amd.com>, <ruifeng.wang@arm.com>,\n <konstantin.ananyev@intel.com>, <radu.nicolau@intel.com>,\n <ajit.khaparde@broadcom.com>, <rnagadheeraj@marvell.com>,\n <adwivedi@marvell.com>, <ciara.power@intel.com>,\n Akhil Goyal <gakhil@marvell.com>, Rebecca Troy <rebecca.troy@intel.com>", "Date": "Mon, 18 Oct 2021 20:12:01 +0530", "Message-ID": "<20211018144201.2028022-8-gakhil@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211018144201.2028022-1-gakhil@marvell.com>", "References": "<20211011124309.4066491-1-gakhil@marvell.com>\n <20211018144201.2028022-1-gakhil@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "Y1cId9Mg-3GWu_vQlvkSIL183r-eV0XV", "X-Proofpoint-ORIG-GUID": "Y1cId9Mg-3GWu_vQlvkSIL183r-eV0XV", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475\n definitions=2021-10-18_06,2021-10-18_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH v3 7/7] cryptodev: move device specific structures", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The device specific structures - rte_cryptodev\nand rte_cryptodev_data are moved to cryptodev_pmd.h\nto hide it from the applications.\n\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\nTested-by: Rebecca Troy <rebecca.troy@intel.com>\nAcked-by: Fan Zhang <roy.fan.zhang@intel.com>\n---\n drivers/crypto/ccp/ccp_dev.h | 2 +-\n drivers/crypto/cnxk/cn10k_ipsec.c | 2 +-\n drivers/crypto/cnxk/cn9k_ipsec.c | 2 +-\n .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 2 +-\n drivers/crypto/cnxk/cnxk_cryptodev_sec.c | 2 +-\n drivers/crypto/nitrox/nitrox_sym_reqmgr.c | 2 +-\n drivers/crypto/octeontx/otx_cryptodev.c | 1 -\n .../crypto/octeontx/otx_cryptodev_hw_access.c | 2 +-\n .../crypto/octeontx/otx_cryptodev_hw_access.h | 2 +-\n drivers/crypto/octeontx/otx_cryptodev_ops.h | 2 +-\n .../crypto/octeontx2/otx2_cryptodev_mbox.c | 2 +-\n drivers/crypto/scheduler/scheduler_failover.c | 2 +-\n .../crypto/scheduler/scheduler_multicore.c | 2 +-\n .../scheduler/scheduler_pkt_size_distr.c | 2 +-\n .../crypto/scheduler/scheduler_roundrobin.c | 2 +-\n drivers/event/cnxk/cnxk_eventdev.h | 2 +-\n drivers/event/dpaa/dpaa_eventdev.c | 2 +-\n drivers/event/dpaa2/dpaa2_eventdev.c | 2 +-\n drivers/event/octeontx/ssovf_evdev.c | 2 +-\n .../event/octeontx2/otx2_evdev_crypto_adptr.c | 2 +-\n lib/cryptodev/cryptodev_pmd.h | 65 ++++++++++++++++++\n lib/cryptodev/rte_cryptodev_core.h | 67 -------------------\n lib/cryptodev/version.map | 2 +-\n 23 files changed, 85 insertions(+), 88 deletions(-)", "diff": "diff --git a/drivers/crypto/ccp/ccp_dev.h b/drivers/crypto/ccp/ccp_dev.h\nindex ca5145c278..85c8fc47a2 100644\n--- a/drivers/crypto/ccp/ccp_dev.h\n+++ b/drivers/crypto/ccp/ccp_dev.h\n@@ -17,7 +17,7 @@\n #include <rte_pci.h>\n #include <rte_spinlock.h>\n #include <rte_crypto_sym.h>\n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n \n /**< CCP sspecific */\n #define MAX_HW_QUEUES 5\ndiff --git a/drivers/crypto/cnxk/cn10k_ipsec.c b/drivers/crypto/cnxk/cn10k_ipsec.c\nindex defc792aa8..27df1dcd64 100644\n--- a/drivers/crypto/cnxk/cn10k_ipsec.c\n+++ b/drivers/crypto/cnxk/cn10k_ipsec.c\n@@ -3,7 +3,7 @@\n */\n \n #include <rte_malloc.h>\n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_esp.h>\n #include <rte_ip.h>\n #include <rte_security.h>\ndiff --git a/drivers/crypto/cnxk/cn9k_ipsec.c b/drivers/crypto/cnxk/cn9k_ipsec.c\nindex 9ca4d20c62..53fb793654 100644\n--- a/drivers/crypto/cnxk/cn9k_ipsec.c\n+++ b/drivers/crypto/cnxk/cn9k_ipsec.c\n@@ -2,7 +2,7 @@\n * Copyright(C) 2021 Marvell.\n */\n \n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_ip.h>\n #include <rte_security.h>\n #include <rte_security_driver.h>\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\nindex a227e6981c..a53b489a04 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\n@@ -2,7 +2,7 @@\n * Copyright(C) 2021 Marvell.\n */\n \n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_security.h>\n \n #include \"roc_api.h\"\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_sec.c b/drivers/crypto/cnxk/cnxk_cryptodev_sec.c\nindex 8d04d4b575..2021d5c77e 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_sec.c\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_sec.c\n@@ -2,7 +2,7 @@\n * Copyright(C) 2021 Marvell.\n */\n \n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_malloc.h>\n #include <rte_security.h>\n #include <rte_security_driver.h>\ndiff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\nindex fe3ca25a0c..9edb0cc00f 100644\n--- a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\n+++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\n@@ -3,7 +3,7 @@\n */\n \n #include <rte_crypto.h>\n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_cycles.h>\n #include <rte_errno.h>\n \ndiff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c\nindex 05b78329d6..337d06aab8 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev.c\n@@ -4,7 +4,6 @@\n \n #include <rte_bus_pci.h>\n #include <rte_common.h>\n-#include <rte_cryptodev.h>\n #include <cryptodev_pmd.h>\n #include <rte_log.h>\n #include <rte_pci.h>\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\nindex 7b89a62d81..20b288334a 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n@@ -7,7 +7,7 @@\n \n #include <rte_branch_prediction.h>\n #include <rte_common.h>\n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_errno.h>\n #include <rte_mempool.h>\n #include <rte_memzone.h>\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\nindex 7c6b1e45b4..e48805fb09 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n@@ -7,7 +7,7 @@\n #include <stdbool.h>\n \n #include <rte_branch_prediction.h>\n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_cycles.h>\n #include <rte_io.h>\n #include <rte_memory.h>\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h\nindex f234f16970..83b82ea059 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_ops.h\n+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h\n@@ -5,7 +5,7 @@\n #ifndef _OTX_CRYPTODEV_OPS_H_\n #define _OTX_CRYPTODEV_OPS_H_\n \n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n \n #define OTX_CPT_MIN_HEADROOM_REQ\t(24)\n #define OTX_CPT_MIN_TAILROOM_REQ\t(8)\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\nindex 1a8edae7eb..f9e7b0b474 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n@@ -1,7 +1,7 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n * Copyright (C) 2019 Marvell International Ltd.\n */\n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_ethdev.h>\n \n #include \"otx2_cryptodev.h\"\ndiff --git a/drivers/crypto/scheduler/scheduler_failover.c b/drivers/crypto/scheduler/scheduler_failover.c\nindex 844312dd1b..5023577ef8 100644\n--- a/drivers/crypto/scheduler/scheduler_failover.c\n+++ b/drivers/crypto/scheduler/scheduler_failover.c\n@@ -2,7 +2,7 @@\n * Copyright(c) 2017 Intel Corporation\n */\n \n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_malloc.h>\n \n #include \"rte_cryptodev_scheduler_operations.h\"\ndiff --git a/drivers/crypto/scheduler/scheduler_multicore.c b/drivers/crypto/scheduler/scheduler_multicore.c\nindex 1e2e8dbf9f..900ab4049d 100644\n--- a/drivers/crypto/scheduler/scheduler_multicore.c\n+++ b/drivers/crypto/scheduler/scheduler_multicore.c\n@@ -3,7 +3,7 @@\n */\n #include <unistd.h>\n \n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_malloc.h>\n \n #include \"rte_cryptodev_scheduler_operations.h\"\ndiff --git a/drivers/crypto/scheduler/scheduler_pkt_size_distr.c b/drivers/crypto/scheduler/scheduler_pkt_size_distr.c\nindex 57e330a744..933a5c6978 100644\n--- a/drivers/crypto/scheduler/scheduler_pkt_size_distr.c\n+++ b/drivers/crypto/scheduler/scheduler_pkt_size_distr.c\n@@ -2,7 +2,7 @@\n * Copyright(c) 2017 Intel Corporation\n */\n \n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_malloc.h>\n \n #include \"rte_cryptodev_scheduler_operations.h\"\ndiff --git a/drivers/crypto/scheduler/scheduler_roundrobin.c b/drivers/crypto/scheduler/scheduler_roundrobin.c\nindex bc4a632106..ace2dec2ec 100644\n--- a/drivers/crypto/scheduler/scheduler_roundrobin.c\n+++ b/drivers/crypto/scheduler/scheduler_roundrobin.c\n@@ -2,7 +2,7 @@\n * Copyright(c) 2017 Intel Corporation\n */\n \n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_malloc.h>\n \n #include \"rte_cryptodev_scheduler_operations.h\"\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 8a5c737e4b..b57004c0dc 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -7,7 +7,7 @@\n \n #include <string.h>\n \n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_devargs.h>\n #include <rte_ethdev.h>\n #include <rte_event_eth_rx_adapter.h>\ndiff --git a/drivers/event/dpaa/dpaa_eventdev.c b/drivers/event/dpaa/dpaa_eventdev.c\nindex ec74160325..1d7ddfe1d1 100644\n--- a/drivers/event/dpaa/dpaa_eventdev.c\n+++ b/drivers/event/dpaa/dpaa_eventdev.c\n@@ -28,7 +28,7 @@\n #include <rte_ethdev.h>\n #include <rte_event_eth_rx_adapter.h>\n #include <rte_event_eth_tx_adapter.h>\n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_dpaa_bus.h>\n #include <rte_dpaa_logs.h>\n #include <rte_cycles.h>\ndiff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c\nindex 5ccf22f77f..e03afb2958 100644\n--- a/drivers/event/dpaa2/dpaa2_eventdev.c\n+++ b/drivers/event/dpaa2/dpaa2_eventdev.c\n@@ -25,7 +25,7 @@\n #include <rte_pci.h>\n #include <rte_bus_vdev.h>\n #include <ethdev_driver.h>\n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_event_eth_rx_adapter.h>\n #include <rte_event_eth_tx_adapter.h>\n \ndiff --git a/drivers/event/octeontx/ssovf_evdev.c b/drivers/event/octeontx/ssovf_evdev.c\nindex b93f6ec8c6..9846fce34b 100644\n--- a/drivers/event/octeontx/ssovf_evdev.c\n+++ b/drivers/event/octeontx/ssovf_evdev.c\n@@ -5,7 +5,7 @@\n #include <inttypes.h>\n \n #include <rte_common.h>\n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_debug.h>\n #include <rte_dev.h>\n #include <rte_eal.h>\ndiff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\nindex d9a002625c..d59d6c53f6 100644\n--- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\n+++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\n@@ -2,7 +2,7 @@\n * Copyright (C) 2020-2021 Marvell.\n */\n \n-#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n #include <rte_eventdev.h>\n \n #include \"otx2_cryptodev.h\"\ndiff --git a/lib/cryptodev/cryptodev_pmd.h b/lib/cryptodev/cryptodev_pmd.h\nindex 9bb1e47ae4..89bf2af399 100644\n--- a/lib/cryptodev/cryptodev_pmd.h\n+++ b/lib/cryptodev/cryptodev_pmd.h\n@@ -52,6 +52,71 @@ struct rte_cryptodev_pmd_init_params {\n \tunsigned int max_nb_queue_pairs;\n };\n \n+/**\n+ * @internal\n+ * The data part, with no function pointers, associated with each device.\n+ *\n+ * This structure is safe to place in shared memory to be common among\n+ * different processes in a multi-process configuration.\n+ */\n+struct rte_cryptodev_data {\n+\t/** Device ID for this instance */\n+\tuint8_t dev_id;\n+\t/** Socket ID where memory is allocated */\n+\tuint8_t socket_id;\n+\t/** Unique identifier name */\n+\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n+\n+\t__extension__\n+\t/** Device state: STARTED(1)/STOPPED(0) */\n+\tuint8_t dev_started : 1;\n+\n+\t/** Session memory pool */\n+\tstruct rte_mempool *session_pool;\n+\t/** Array of pointers to queue pairs. */\n+\tvoid **queue_pairs;\n+\t/** Number of device queue pairs. */\n+\tuint16_t nb_queue_pairs;\n+\n+\t/** PMD-specific private data */\n+\tvoid *dev_private;\n+} __rte_cache_aligned;\n+\n+/** @internal The data structure associated with each crypto device. */\n+struct rte_cryptodev {\n+\t/** Pointer to PMD dequeue function. */\n+\tdequeue_pkt_burst_t dequeue_burst;\n+\t/** Pointer to PMD enqueue function. */\n+\tenqueue_pkt_burst_t enqueue_burst;\n+\n+\t/** Pointer to device data */\n+\tstruct rte_cryptodev_data *data;\n+\t/** Functions exported by PMD */\n+\tstruct rte_cryptodev_ops *dev_ops;\n+\t/** Feature flags exposes HW/SW features for the given device */\n+\tuint64_t feature_flags;\n+\t/** Backing device */\n+\tstruct rte_device *device;\n+\n+\t/** Crypto driver identifier*/\n+\tuint8_t driver_id;\n+\n+\t/** User application callback for interrupts if present */\n+\tstruct rte_cryptodev_cb_list link_intr_cbs;\n+\n+\t/** Context for security ops */\n+\tvoid *security_ctx;\n+\n+\t__extension__\n+\t/** Flag indicating the device is attached */\n+\tuint8_t attached : 1;\n+\n+\t/** User application callback for pre enqueue processing */\n+\tstruct rte_cryptodev_cb_rcu *enq_cbs;\n+\t/** User application callback for post dequeue processing */\n+\tstruct rte_cryptodev_cb_rcu *deq_cbs;\n+} __rte_cache_aligned;\n+\n /** Global structure used for maintaining state of allocated crypto devices */\n struct rte_cryptodev_global {\n \tstruct rte_cryptodev *devs;\t/**< Device information array */\ndiff --git a/lib/cryptodev/rte_cryptodev_core.h b/lib/cryptodev/rte_cryptodev_core.h\nindex e9e9a44b3c..c13e214439 100644\n--- a/lib/cryptodev/rte_cryptodev_core.h\n+++ b/lib/cryptodev/rte_cryptodev_core.h\n@@ -54,73 +54,6 @@ struct rte_crypto_fp_ops {\n \n extern struct rte_crypto_fp_ops rte_crypto_fp_ops[RTE_CRYPTO_MAX_DEVS];\n \n-/**\n- * @internal\n- * The data part, with no function pointers, associated with each device.\n- *\n- * This structure is safe to place in shared memory to be common among\n- * different processes in a multi-process configuration.\n- */\n-struct rte_cryptodev_data {\n-\tuint8_t dev_id;\n-\t/**< Device ID for this instance */\n-\tuint8_t socket_id;\n-\t/**< Socket ID where memory is allocated */\n-\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n-\t/**< Unique identifier name */\n-\n-\t__extension__\n-\tuint8_t dev_started : 1;\n-\t/**< Device state: STARTED(1)/STOPPED(0) */\n-\n-\tstruct rte_mempool *session_pool;\n-\t/**< Session memory pool */\n-\tvoid **queue_pairs;\n-\t/**< Array of pointers to queue pairs. */\n-\tuint16_t nb_queue_pairs;\n-\t/**< Number of device queue pairs. */\n-\n-\tvoid *dev_private;\n-\t/**< PMD-specific private data */\n-} __rte_cache_aligned;\n-\n-\n-/** @internal The data structure associated with each crypto device. */\n-struct rte_cryptodev {\n-\tdequeue_pkt_burst_t dequeue_burst;\n-\t/**< Pointer to PMD receive function. */\n-\tenqueue_pkt_burst_t enqueue_burst;\n-\t/**< Pointer to PMD transmit function. */\n-\n-\tstruct rte_cryptodev_data *data;\n-\t/**< Pointer to device data */\n-\tstruct rte_cryptodev_ops *dev_ops;\n-\t/**< Functions exported by PMD */\n-\tuint64_t feature_flags;\n-\t/**< Feature flags exposes HW/SW features for the given device */\n-\tstruct rte_device *device;\n-\t/**< Backing device */\n-\n-\tuint8_t driver_id;\n-\t/**< Crypto driver identifier*/\n-\n-\tstruct rte_cryptodev_cb_list link_intr_cbs;\n-\t/**< User application callback for interrupts if present */\n-\n-\tvoid *security_ctx;\n-\t/**< Context for security ops */\n-\n-\t__extension__\n-\tuint8_t attached : 1;\n-\t/**< Flag indicating the device is attached */\n-\n-\tstruct rte_cryptodev_cb_rcu *enq_cbs;\n-\t/**< User application callback for pre enqueue processing */\n-\n-\tstruct rte_cryptodev_cb_rcu *deq_cbs;\n-\t/**< User application callback for post dequeue processing */\n-} __rte_cache_aligned;\n-\n /**\n * The pool of rte_cryptodev structures.\n */\ndiff --git a/lib/cryptodev/version.map b/lib/cryptodev/version.map\nindex 157dac521d..b55b4b8e7e 100644\n--- a/lib/cryptodev/version.map\n+++ b/lib/cryptodev/version.map\n@@ -43,7 +43,6 @@ DPDK_22 {\n \trte_cryptodev_sym_session_create;\n \trte_cryptodev_sym_session_free;\n \trte_cryptodev_sym_session_init;\n-\trte_cryptodevs;\n \n \t#added in 21.11\n \trte_crypto_fp_ops;\n@@ -125,4 +124,5 @@ INTERNAL {\n \trte_cryptodev_pmd_parse_input_args;\n \trte_cryptodev_pmd_probing_finish;\n \trte_cryptodev_pmd_release_device;\n+\trte_cryptodevs;\n };\n", "prefixes": [ "v3", "7/7" ] }