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GET /api/patches/101463/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 101463,
    "url": "http://patches.dpdk.org/api/patches/101463/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211013182720.32486-10-hemant.agrawal@nxp.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211013182720.32486-10-hemant.agrawal@nxp.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211013182720.32486-10-hemant.agrawal@nxp.com",
    "date": "2021-10-13T18:27:14",
    "name": "[v3,09/15] crypto/dpaa2_sec: support OOP with raw buffer API",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "ccba3f00de6ea4a4f10250133c9ea5c487744578",
    "submitter": {
        "id": 477,
        "url": "http://patches.dpdk.org/api/people/477/?format=api",
        "name": "Hemant Agrawal",
        "email": "hemant.agrawal@nxp.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211013182720.32486-10-hemant.agrawal@nxp.com/mbox/",
    "series": [
        {
            "id": 19612,
            "url": "http://patches.dpdk.org/api/series/19612/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19612",
            "date": "2021-10-13T18:27:05",
            "name": "crypto: add raw vector support in DPAAx",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/19612/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/101463/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/101463/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Hemant Agrawal <hemant.agrawal@nxp.com>",
        "To": "dev@dpdk.org,\n\tgakhil@marvell.com",
        "Cc": "roy.fan.zhang@intel.com, konstantin.ananyev@intel.com,\n Gagandeep Singh <g.singh@nxp.com>",
        "Date": "Wed, 13 Oct 2021 23:57:14 +0530",
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        "Subject": "[dpdk-dev] [PATCH v3 09/15] crypto/dpaa2_sec: support OOP with raw\n buffer API",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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    },
    "content": "From: Gagandeep Singh <g.singh@nxp.com>\n\nadd support for out of order processing with raw vector APIs.\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\n---\n drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h   |   1 +\n drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c | 156 +++++++++++++++-----\n 2 files changed, 116 insertions(+), 41 deletions(-)",
    "diff": "diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\nindex f397b756e8..05bd7c0736 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\n@@ -179,6 +179,7 @@ typedef int (*dpaa2_sec_build_fd_t)(\n \n typedef int (*dpaa2_sec_build_raw_dp_fd_t)(uint8_t *drv_ctx,\n \t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_sgl *dest_sgl,\n \t\t       struct rte_crypto_va_iova_ptr *iv,\n \t\t       struct rte_crypto_va_iova_ptr *digest,\n \t\t       struct rte_crypto_va_iova_ptr *auth_iv,\ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\nindex 5c29c61f9d..4f78cef9c0 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\n@@ -24,6 +24,7 @@ struct dpaa2_sec_raw_dp_ctx {\n static int\n build_raw_dp_chain_fd(uint8_t *drv_ctx,\n \t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_sgl *dest_sgl,\n \t\t       struct rte_crypto_va_iova_ptr *iv,\n \t\t       struct rte_crypto_va_iova_ptr *digest,\n \t\t       struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -89,17 +90,33 @@ build_raw_dp_chain_fd(uint8_t *drv_ctx,\n \t\t\t(cipher_len + icv_len) :\n \t\t\tcipher_len;\n \n-\t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.auth.head);\n-\tsge->length = sgl->vec[0].len - ofs.ofs.auth.head;\n+\t/* OOP */\n+\tif (dest_sgl) {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tsge->length = dest_sgl->vec[0].len - ofs.ofs.cipher.head;\n \n-\t/* o/p segs */\n-\tfor (i = 1; i < sgl->num; i++) {\n-\t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\t\tsge->length = sgl->vec[i].len;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = dest_sgl->vec[i].len;\n+\t\t}\n+\t} else {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tsge->length = sgl->vec[0].len - ofs.ofs.cipher.head;\n+\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = sgl->vec[i].len;\n+\t\t}\n \t}\n \n \tif (sess->dir == DIR_ENC) {\n@@ -160,6 +177,7 @@ build_raw_dp_chain_fd(uint8_t *drv_ctx,\n static int\n build_raw_dp_aead_fd(uint8_t *drv_ctx,\n \t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_sgl *dest_sgl,\n \t\t       struct rte_crypto_va_iova_ptr *iv,\n \t\t       struct rte_crypto_va_iova_ptr *digest,\n \t\t       struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -219,17 +237,33 @@ build_raw_dp_aead_fd(uint8_t *drv_ctx,\n \t\t\t(aead_len + icv_len) :\n \t\t\taead_len;\n \n-\t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n-\tsge->length = sgl->vec[0].len - ofs.ofs.cipher.head;\n+\t/* OOP */\n+\tif (dest_sgl) {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tsge->length = dest_sgl->vec[0].len - ofs.ofs.cipher.head;\n \n-\t/* o/p segs */\n-\tfor (i = 1; i < sgl->num; i++) {\n-\t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\t\tsge->length = sgl->vec[i].len;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = dest_sgl->vec[i].len;\n+\t\t}\n+\t} else {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tsge->length = sgl->vec[0].len - ofs.ofs.cipher.head;\n+\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = sgl->vec[i].len;\n+\t\t}\n \t}\n \n \tif (sess->dir == DIR_ENC) {\n@@ -294,6 +328,7 @@ build_raw_dp_aead_fd(uint8_t *drv_ctx,\n static int\n build_raw_dp_auth_fd(uint8_t *drv_ctx,\n \t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_sgl *dest_sgl,\n \t\t       struct rte_crypto_va_iova_ptr *iv,\n \t\t       struct rte_crypto_va_iova_ptr *digest,\n \t\t       struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -303,6 +338,7 @@ build_raw_dp_auth_fd(uint8_t *drv_ctx,\n {\n \tRTE_SET_USED(iv);\n \tRTE_SET_USED(auth_iv);\n+\tRTE_SET_USED(dest_sgl);\n \n \tdpaa2_sec_session *sess =\n \t\t((struct dpaa2_sec_raw_dp_ctx *)drv_ctx)->session;\n@@ -416,6 +452,7 @@ build_raw_dp_auth_fd(uint8_t *drv_ctx,\n static int\n build_raw_dp_proto_fd(uint8_t *drv_ctx,\n \t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_sgl *dest_sgl,\n \t\t       struct rte_crypto_va_iova_ptr *iv,\n \t\t       struct rte_crypto_va_iova_ptr *digest,\n \t\t       struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -466,20 +503,39 @@ build_raw_dp_proto_fd(uint8_t *drv_ctx,\n \tDPAA2_SET_FLE_SG_EXT(op_fle);\n \tDPAA2_SET_FLE_ADDR(op_fle, DPAA2_VADDR_TO_IOVA(sge));\n \n-\t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\tsge->length = sgl->vec[0].len;\n-\tout_len += sge->length;\n-\t/* o/p segs */\n-\tfor (i = 1; i < sgl->num; i++) {\n-\t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t/* OOP */\n+\tif (dest_sgl) {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n \t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\t\tsge->length = sgl->vec[i].len;\n+\t\tsge->length = dest_sgl->vec[0].len;\n+\t\tout_len += sge->length;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = dest_sgl->vec[i].len;\n+\t\t\tout_len += sge->length;\n+\t\t}\n+\t\tsge->length = dest_sgl->vec[i - 1].tot_len;\n+\n+\t} else {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\tsge->length = sgl->vec[0].len;\n \t\tout_len += sge->length;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = sgl->vec[i].len;\n+\t\t\tout_len += sge->length;\n+\t\t}\n+\t\tsge->length = sgl->vec[i - 1].tot_len;\n \t}\n-\tsge->length = sgl->vec[i - 1].tot_len;\n \tout_len += sge->length;\n \n \tDPAA2_SET_FLE_FIN(sge);\n@@ -528,6 +584,7 @@ build_raw_dp_proto_fd(uint8_t *drv_ctx,\n static int\n build_raw_dp_cipher_fd(uint8_t *drv_ctx,\n \t\t       struct rte_crypto_sgl *sgl,\n+\t\t       struct rte_crypto_sgl *dest_sgl,\n \t\t       struct rte_crypto_va_iova_ptr *iv,\n \t\t       struct rte_crypto_va_iova_ptr *digest,\n \t\t       struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -593,17 +650,33 @@ build_raw_dp_cipher_fd(uint8_t *drv_ctx,\n \top_fle->length = data_len;\n \tDPAA2_SET_FLE_SG_EXT(op_fle);\n \n-\t/* o/p 1st seg */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n-\tsge->length = sgl->vec[0].len - data_offset;\n+\t/* OOP */\n+\tif (dest_sgl) {\n+\t\t/* o/p 1st seg */\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n+\t\tsge->length = dest_sgl->vec[0].len - data_offset;\n \n-\t/* o/p segs */\n-\tfor (i = 1; i < sgl->num; i++) {\n-\t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\t\tsge->length = sgl->vec[i].len;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = dest_sgl->vec[i].len;\n+\t\t}\n+\t} else {\n+\t\t/* o/p 1st seg */\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n+\t\tsge->length = sgl->vec[0].len - data_offset;\n+\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = sgl->vec[i].len;\n+\t\t}\n \t}\n \tDPAA2_SET_FLE_FIN(sge);\n \n@@ -706,6 +779,7 @@ dpaa2_sec_raw_enqueue_burst(void *qp_data, uint8_t *drv_ctx,\n \t\t\tmemset(&fd_arr[loop], 0, sizeof(struct qbman_fd));\n \t\t\tret = sess->build_raw_dp_fd(drv_ctx,\n \t\t\t\t\t\t    &vec->src_sgl[loop],\n+\t\t\t\t\t\t    &vec->dest_sgl[loop],\n \t\t\t\t\t\t    &vec->iv[loop],\n \t\t\t\t\t\t    &vec->digest[loop],\n \t\t\t\t\t\t    &vec->auth_iv[loop],\n",
    "prefixes": [
        "v3",
        "09/15"
    ]
}