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GET /api/patches/100634/?format=api
{ "id": 100634, "url": "http://patches.dpdk.org/api/patches/100634/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211006120945.6612-12-talshn@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211006120945.6612-12-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211006120945.6612-12-talshn@nvidia.com", "date": "2021-10-06T12:09:44", "name": "[11/12] common/mlx5: read FCS scattering capability from DevX", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cedfff0a99eb7d92e5262d90b4dc3f7ca62a4766", "submitter": { "id": 1893, "url": "http://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211006120945.6612-12-talshn@nvidia.com/mbox/", "series": [ { "id": 19415, "url": "http://patches.dpdk.org/api/series/19415/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19415", "date": "2021-10-06T12:09:33", "name": "Expand NIC offloads support on Windows", "version": 1, "mbox": "http://patches.dpdk.org/series/19415/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/100634/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/100634/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3C22BA0C41;\n\tWed, 6 Oct 2021 14:12:49 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AA9AE4148E;\n\tWed, 6 Oct 2021 14:11:09 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2079.outbound.protection.outlook.com [40.107.223.79])\n by mails.dpdk.org (Postfix) with ESMTP id 90EB041470\n for <dev@dpdk.org>; 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dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Tal Shnaiderman <talshn@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <matan@nvidia.com>, <rasland@nvidia.com>,\n <asafp@nvidia.com>, <viacheslavo@nvidia.com>, <eilong@nvidia.com>,\n <kcollins@nvidia.com>, <idanhac@nvidia.com>", "Date": "Wed, 6 Oct 2021 15:09:44 +0300", "Message-ID": "<20211006120945.6612-12-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20211006120945.6612-1-talshn@nvidia.com>", "References": "<20211006120945.6612-1-talshn@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "8eb97027-7cf7-4250-e33a-08d988c2601b", "X-MS-TrafficTypeDiagnostic": "MWHPR12MB1408:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <MWHPR12MB140840C497EAD6EDB474E95EA4B09@MWHPR12MB1408.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2733;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 2n1HVwb0c89Eg6avofPtfp5mE9FKn+1KptIW6U9r/Bdz8V15Xoue1Wvu81YJxGBBGScfvtARu6c9nmpuv1/9619YHsCGos8cERBoU1pLbdR2VS38iZXgJPyrr4oPw28VI5DHIM9TNOVsN8SrH94lg86IUsiNW0Z8FEwz0Ybl/pRimqRg52JbMtP+1jXjd2RakXHHFjAKqx1ugHsWcWsGEkaengAuw4ST9O8cqCQcq6EzYRpv0JXlWccZYwW3B+yZdH6m/kBOk8M4mRswZNmKRUwAEw23aEyCnTLS5jY7QzyJoUolptVPESSLmUW/OxYfijs55W081sEDL/X01sIGkA0SxrdCJ0lLmbr98dVi+PtRbdnKnq+VkjKagZfE39cIgm/MCnc0nQA8smvTPi+Dhu45McBKNMhyXe3pcXPBuVoom/bYW7RF1lNTZJ7gjfbVoEPDBJSv50Ka4mzlvSNPI6u+HKHIdhbNfaot2B+J6QZws4YRQC47zH/N+2n+qj+i+oDD6QfGCUrx2M7J3QTI32X/7OxWKNcAuwYJUuvtGutti7sX7jA2hhAGSF+Zm9jyrDIg3xtIm5EBqOZNpyVlF/CHk4+5LHTHfI2tZLKYQGsoHW/5ibRc7+k6TcHXqV8pM/mp0mwC1TovGMIVErbowzga/EF0XiBMjY65qATU6hKCnWFCztPjIRYjRUTj61A/5qQY+TXwopIPMdVew6ow/Q==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(8936002)(86362001)(6916009)(7636003)(356005)(4326008)(82310400003)(1076003)(54906003)(8676002)(6286002)(316002)(186003)(16526019)(55016002)(5660300002)(26005)(7696005)(36756003)(6666004)(70586007)(70206006)(47076005)(426003)(36860700001)(107886003)(36906005)(336012)(2616005)(508600001)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2021 12:11:06.5909 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8eb97027-7cf7-4250-e33a-08d988c2601b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT057.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR12MB1408", "Subject": "[dpdk-dev] [PATCH 11/12] common/mlx5: read FCS scattering\n capability from DevX", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "mlx5 in Windows needs the hca capability scatter_fcs\nto query the NIC support for the CRC keeping offload.\n\nAdded the capability as part of the capabilities\nqueried by the PMD using DevX.\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n 2 files changed, 3 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex deee4954f4..33c064a418 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -991,6 +991,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\t\t lro_cap);\n \tattr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,\n \t\t\t\t hcattr, max_lso_cap);\n+\tattr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,\n+\t\t\t\t hcattr, scatter_fcs);\n \tattr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,\n \t\t\t\t\thcattr, tunnel_lro_gre);\n \tattr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex f4aa851cd0..6b9f191a69 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -115,6 +115,7 @@ struct mlx5_hca_attr {\n \tuint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */\n \tuint32_t tunnel_stateless_gtp:1;\n \tuint32_t max_lso_cap;\n+\tuint32_t scatter_fcs:1;\n \tuint32_t lro_cap:1;\n \tuint32_t tunnel_lro_gre:1;\n \tuint32_t tunnel_lro_vxlan:1;\n", "prefixes": [ "11/12" ] }