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GET /api/patches/100633/?format=api
{ "id": 100633, "url": "http://patches.dpdk.org/api/patches/100633/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211006120945.6612-10-talshn@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211006120945.6612-10-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211006120945.6612-10-talshn@nvidia.com", "date": "2021-10-06T12:09:42", "name": "[09/12] common/mlx5: read VLAN capability from DevX", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "efac3145db3d45b866b07b82db4beaa853985025", "submitter": { "id": 1893, "url": "http://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211006120945.6612-10-talshn@nvidia.com/mbox/", "series": [ { "id": 19415, "url": "http://patches.dpdk.org/api/series/19415/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19415", "date": "2021-10-06T12:09:33", "name": "Expand NIC offloads support on Windows", "version": 1, "mbox": "http://patches.dpdk.org/series/19415/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/100633/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/100633/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EC40BA0C41;\n\tWed, 6 Oct 2021 14:12:42 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9F26441141;\n\tWed, 6 Oct 2021 14:11:06 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2050.outbound.protection.outlook.com [40.107.220.50])\n by mails.dpdk.org (Postfix) with ESMTP id 87DA541136\n for <dev@dpdk.org>; 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dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Tal Shnaiderman <talshn@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <matan@nvidia.com>, <rasland@nvidia.com>,\n <asafp@nvidia.com>, <viacheslavo@nvidia.com>, <eilong@nvidia.com>,\n <kcollins@nvidia.com>, <idanhac@nvidia.com>", "Date": "Wed, 6 Oct 2021 15:09:42 +0300", "Message-ID": "<20211006120945.6612-10-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20211006120945.6612-1-talshn@nvidia.com>", "References": "<20211006120945.6612-1-talshn@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "d3b00c06-f8db-4187-be6f-08d988c25e43", "X-MS-TrafficTypeDiagnostic": "DM5PR12MB1531:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <DM5PR12MB15310F974EE3A610492458E7A4B09@DM5PR12MB1531.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2733;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n XLSTcuo96pfcdQM7hHY9/A7RWmMSZbwNRJotwMI53MQrrOJ17Pgj8aiOWM8jZDoRcInkl1ZTVr8YYIjzO9Tr93qloj3M2FGu5KpMq5YHSBIFQ2W5RNN5pRHI9/cXs+HWlAvJybAcqwWAbkRBolQietC5CjN4I4PuAc0gwttKEIPgBiTU5R/aFLDcDeSk1oDN+JSkUkbBGU0CIRjTYxu/u8ivHMvm80P7NM3S+tbF1kJNjindVMnZHwWi5VhbLQH13Mqrh9xOhXwmD2oT8yyji/F18o+DrteSQzYjLX9h3dGplocnVXDI9MSjbAq5J/pkolhhHnmLXHP+uCc3K+F/3YL755DzJo/+HH0+Rs7KtXjOFoCR3Cy/wfJkBpTd5Lm6DEKLfz2RBtJaWRiNesArQwKl0jSm/92+i21iH5PBuQZDUFQJ8TW54RU8csHSZGD/Ei73F3NQInTohNle3K9ii2BZsy4EVcmAeCDf/YyNGx0+c1CKdsMaWrQfzjZxk3lyjRU3eirxPqw8wWHDyupZw7URg8GINRitGVd9KjM/0IL8ywM1TlrGvf7u8Rd9860TOjqvlIgob3hSrNkvqWo/17WFAXta8hl6kXdxSnfOgY1qiZHTdx2FToDleT+6kTL5CyOtAeoTIq05BsXRJ8PndsfaWhooh0Ub46sRC1vnXtPycoi/ub7p5YMpo/nrLjfwB5IAHxcFNqFm6OlzzGBsxQ==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(316002)(6666004)(36756003)(2616005)(1076003)(54906003)(86362001)(8676002)(107886003)(70206006)(70586007)(55016002)(6286002)(5660300002)(186003)(16526019)(82310400003)(6916009)(356005)(7636003)(36860700001)(26005)(2906002)(508600001)(47076005)(426003)(8936002)(7696005)(4326008)(336012);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2021 12:11:03.4797 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d3b00c06-f8db-4187-be6f-08d988c25e43", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT057.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR12MB1531", "Subject": "[dpdk-dev] [PATCH 09/12] common/mlx5: read VLAN capability from DevX", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "mlx5 in Windows needs the hca capability vlan_cap\nto query the NIC for VLAN stripping support\n\nAdded the capability as part of the capabilities\nqueried by the PMD using DevX.\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n 2 files changed, 3 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex be3c3e61d1..deee4954f4 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -985,6 +985,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\t\t\t hcattr, wqe_vlan_insert);\n \tattr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,\n \t\t\t\t\t hcattr, csum_cap);\n+\tattr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,\n+\t\t\t\t\t hcattr, vlan_cap);\n \tattr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,\n \t\t\t\t lro_cap);\n \tattr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 7a0155558e..f4aa851cd0 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -108,6 +108,7 @@ struct mlx5_hca_attr {\n \tuint32_t eth_virt:1;\n \tuint32_t wqe_vlan_insert:1;\n \tuint32_t csum_cap:1;\n+\tuint32_t vlan_cap:1;\n \tuint32_t wqe_inline_mode:2;\n \tuint32_t vport_inline_mode:3;\n \tuint32_t tunnel_stateless_geneve_rx:1;\n", "prefixes": [ "09/12" ] }