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GET /api/patches/100628/?format=api
{ "id": 100628, "url": "http://patches.dpdk.org/api/patches/100628/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211006120945.6612-5-talshn@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211006120945.6612-5-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211006120945.6612-5-talshn@nvidia.com", "date": "2021-10-06T12:09:37", "name": "[04/12] net/mlx5: fix tunneling support query", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "643334929c01d1417013baeecdb1fc57480ff3cc", "submitter": { "id": 1893, "url": "http://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211006120945.6612-5-talshn@nvidia.com/mbox/", "series": [ { "id": 19415, "url": "http://patches.dpdk.org/api/series/19415/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19415", "date": "2021-10-06T12:09:33", "name": "Expand NIC offloads support on Windows", "version": 1, "mbox": "http://patches.dpdk.org/series/19415/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/100628/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/100628/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", 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<kcollins@nvidia.com>, <idanhac@nvidia.com>, <stable@dpdk.org>", "Date": "Wed, 6 Oct 2021 15:09:37 +0300", "Message-ID": "<20211006120945.6612-5-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20211006120945.6612-1-talshn@nvidia.com>", "References": "<20211006120945.6612-1-talshn@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "64903253-9a93-4551-7723-08d988c25556", "X-MS-TrafficTypeDiagnostic": "BN8PR12MB3329:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BN8PR12MB3329B507C6909E06268B5744A4B09@BN8PR12MB3329.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:1169;", "X-MS-Exchange-SenderADCheck": "1", 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CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(83380400001)(82310400003)(8936002)(70586007)(1076003)(8676002)(55016002)(6666004)(6286002)(86362001)(36756003)(36860700001)(5660300002)(6916009)(336012)(26005)(356005)(4326008)(70206006)(508600001)(7636003)(54906003)(7696005)(2906002)(2616005)(426003)(47076005)(16526019)(186003)(316002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2021 12:10:48.5119 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 64903253-9a93-4551-7723-08d988c25556", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT017.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN8PR12MB3329", "Subject": "[dpdk-dev] [PATCH 04/12] net/mlx5: fix tunneling support query", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Currently, the PMD decides if the tunneling offload\ncan enable VXLAN/GRE/GENEVE tunneled TSO support by checking\nconfig->tunnel_en (single bit) and config->tso.\n\nThis is incorrect, the right way is to check the following\nflags returned by the mlx5dv_query_device function:\n\nMLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN - if supported the offload\nDEV_TX_OFFLOAD_VXLAN_TNL_TSO can be enabled.\nMLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE - if supported the offload\nDEV_TX_OFFLOAD_GRE_TNL_TSO can be enabled.\nMLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE - if supported the offload\nDEV_TX_OFFLOAD_GENEVE_TNL_TSO can be enabled.\n\nThe fix enables the offloads according to the correct\nflags returned by the kernel.\n\nFixes: dbccb4cddcd2f7c (\"net/mlx5: convert to new Tx offloads API\")\nCc: stable@dpdk.org\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 28 +++++++++++++++++-----------\n drivers/net/mlx5/linux/mlx5_os.h | 15 +++++++++++++++\n drivers/net/mlx5/mlx5.h | 2 +-\n drivers/net/mlx5/mlx5_txq.c | 24 +++++++++++++++++++-----\n drivers/net/mlx5/windows/mlx5_os.h | 6 ++++++\n 5 files changed, 58 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex a6542629c7..9ac354fabe 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -963,7 +963,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tint err = 0;\n \tunsigned int hw_padding = 0;\n \tunsigned int mps;\n-\tunsigned int tunnel_en = 0;\n \tunsigned int mpls_en = 0;\n \tunsigned int swp = 0;\n \tunsigned int mprq = 0;\n@@ -1145,20 +1144,27 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tconfig->cqe_comp = 1;\n #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n \tif (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {\n-\t\ttunnel_en = ((dv_attr.tunnel_offloads_caps &\n-\t\t\t MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&\n-\t\t\t (dv_attr.tunnel_offloads_caps &\n-\t\t\t MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&\n-\t\t\t (dv_attr.tunnel_offloads_caps &\n-\t\t\t MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));\n-\t}\n-\tDRV_LOG(DEBUG, \"tunnel offloading is %ssupported\",\n-\t\ttunnel_en ? \"\" : \"not \");\n+\t\tconfig->tunnel_en = dv_attr.tunnel_offloads_caps &\n+\t\t\t (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN |\n+\t\t\t MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE |\n+\t\t\t MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE);\n+\t}\n+\tif (config->tunnel_en) {\n+\t\tDRV_LOG(DEBUG, \"tunnel offloading is supported for %s%s%s\",\n+\t\tconfig->tunnel_en &\n+\t\tMLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? \"[VXLAN]\" : \"\",\n+\t\tconfig->tunnel_en &\n+\t\tMLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? \"[GRE]\" : \"\",\n+\t\tconfig->tunnel_en &\n+\t\tMLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? \"[GENEVE]\" : \"\"\n+\t\t);\n+\t} else {\n+\t\tDRV_LOG(DEBUG, \"tunnel offloading is not supported\");\n+\t}\n #else\n \tDRV_LOG(WARNING,\n \t\t\"tunnel offloading disabled due to old OFED/rdma-core version\");\n #endif\n-\tconfig->tunnel_en = tunnel_en;\n #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT\n \tmpls_en = ((dv_attr.tunnel_offloads_caps &\n \t\t MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h\nindex da036edb72..80c70d713a 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.h\n+++ b/drivers/net/mlx5/linux/mlx5_os.h\n@@ -33,4 +33,19 @@ enum mlx5_sw_parsing_offloads {\n \tMLX5_SW_PARSING_TSO_CAP = 0,\n #endif\n };\n+\n+enum mlx5_tunnel_offloads {\n+#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n+\tMLX5_TUNNELED_OFFLOADS_VXLAN_CAP =\n+\t\tMLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN,\n+\tMLX5_TUNNELED_OFFLOADS_GRE_CAP =\n+\t\tMLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE,\n+\tMLX5_TUNNELED_OFFLOADS_GENEVE_CAP =\n+\t\tMLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE,\n+#else\n+\tMLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 0,\n+\tMLX5_TUNNELED_OFFLOADS_GRE_CAP\t = 0,\n+\tMLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 0,\n+#endif\n+};\n #endif /* RTE_PMD_MLX5_OS_H_ */\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 0694927457..58f12cd75c 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -244,7 +244,7 @@ struct mlx5_dev_config {\n \tunsigned int hw_padding:1; /* End alignment padding is supported. */\n \tunsigned int vf:1; /* This is a VF. */\n \tunsigned int sf:1; /* This is a SF. */\n-\tunsigned int tunnel_en:1;\n+\tunsigned int tunnel_en:3;\n \t/* Whether tunnel stateless offloads are supported. */\n \tunsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */\n \tunsigned int cqe_comp:1; /* CQE compression is enabled. */\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 8dca2b7f79..54f42292ac 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -120,10 +120,17 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)\n \tif (config->tunnel_en) {\n \t\tif (config->hw_csum)\n \t\t\toffloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;\n-\t\tif (config->tso)\n-\t\t\toffloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |\n-\t\t\t\t DEV_TX_OFFLOAD_GRE_TNL_TSO |\n-\t\t\t\t DEV_TX_OFFLOAD_GENEVE_TNL_TSO);\n+\t\tif (config->tso) {\n+\t\t\tif (config->tunnel_en &\n+\t\t\t\tMLX5_TUNNELED_OFFLOADS_VXLAN_CAP)\n+\t\t\t\toffloads |= DEV_TX_OFFLOAD_VXLAN_TNL_TSO;\n+\t\t\tif (config->tunnel_en &\n+\t\t\t\tMLX5_TUNNELED_OFFLOADS_GRE_CAP)\n+\t\t\t\toffloads |= DEV_TX_OFFLOAD_GRE_TNL_TSO;\n+\t\t\tif (config->tunnel_en &\n+\t\t\t\tMLX5_TUNNELED_OFFLOADS_GENEVE_CAP)\n+\t\t\t\toffloads |= DEV_TX_OFFLOAD_GENEVE_TNL_TSO;\n+\t\t}\n \t}\n \tif (!config->mprq.enabled)\n \t\toffloads |= DEV_TX_OFFLOAD_MBUF_FAST_FREE;\n@@ -978,7 +985,14 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)\n \t\t\t\t\t\t MLX5_MAX_TSO_HEADER);\n \t\ttxq_ctrl->txq.tso_en = 1;\n \t}\n-\ttxq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;\n+\tif (((DEV_TX_OFFLOAD_VXLAN_TNL_TSO & txq_ctrl->txq.offloads) &&\n+\t (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)) |\n+\t ((DEV_TX_OFFLOAD_GRE_TNL_TSO & txq_ctrl->txq.offloads) &&\n+\t (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GRE_CAP)) |\n+\t ((DEV_TX_OFFLOAD_GENEVE_TNL_TSO & txq_ctrl->txq.offloads) &&\n+\t (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)) |\n+\t (config->swp & MLX5_SW_PARSING_TSO_CAP))\n+\t\ttxq_ctrl->txq.tunnel_en = 1;\n \ttxq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO |\n \t\t\t\t DEV_TX_OFFLOAD_UDP_TNL_TSO) &\n \t\t\t\t txq_ctrl->txq.offloads) && (config->swp &\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h\nindex 6de683357c..8b58265687 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.h\n+++ b/drivers/net/mlx5/windows/mlx5_os.h\n@@ -22,4 +22,10 @@ enum mlx5_sw_parsing_offloads {\n \tMLX5_SW_PARSING_TSO_CAP = 1 << 2,\n };\n \n+enum mlx5_tunnel_offloads {\n+\tMLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 1 << 0,\n+\tMLX5_TUNNELED_OFFLOADS_GRE_CAP\t = 1 << 1,\n+\tMLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 1 << 2,\n+};\n+\n #endif /* RTE_PMD_MLX5_OS_H_ */\n", "prefixes": [ "04/12" ] }