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GET /api/patches/100627/?format=api
{ "id": 100627, "url": "http://patches.dpdk.org/api/patches/100627/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211006120945.6612-4-talshn@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211006120945.6612-4-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211006120945.6612-4-talshn@nvidia.com", "date": "2021-10-06T12:09:36", "name": "[03/12] net/mlx5: query software parsing support on Windows", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "53518f589cbee4b865709722589b5cf888931080", "submitter": { "id": 1893, "url": "http://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211006120945.6612-4-talshn@nvidia.com/mbox/", "series": [ { "id": 19415, "url": "http://patches.dpdk.org/api/series/19415/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19415", "date": "2021-10-06T12:09:33", "name": "Expand NIC offloads support on Windows", "version": 1, "mbox": "http://patches.dpdk.org/series/19415/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/100627/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/100627/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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<kcollins@nvidia.com>, <idanhac@nvidia.com>", "Date": "Wed, 6 Oct 2021 15:09:36 +0300", "Message-ID": "<20211006120945.6612-4-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20211006120945.6612-1-talshn@nvidia.com>", "References": "<20211006120945.6612-1-talshn@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "c71ae8d8-bfad-44da-0096-08d988c253f1", "X-MS-TrafficTypeDiagnostic": "CY4PR12MB1733:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <CY4PR12MB17331BAF49338BF14F6DD5D9A4B09@CY4PR12MB1733.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:5516;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": 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SFS:(4636009)(46966006)(36840700001)(508600001)(6666004)(8936002)(316002)(4326008)(83380400001)(426003)(107886003)(6286002)(7636003)(54906003)(55016002)(86362001)(2616005)(6916009)(356005)(70586007)(47076005)(36860700001)(7696005)(186003)(8676002)(336012)(1076003)(16526019)(82310400003)(26005)(36756003)(2906002)(70206006)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2021 12:10:46.1892 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c71ae8d8-bfad-44da-0096-08d988c253f1", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT017.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR12MB1733", "Subject": "[dpdk-dev] [PATCH 03/12] net/mlx5: query software parsing support\n on Windows", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Query software parsing supported on the NIC.\n\nSave the offloads values in a config parameter.\nThis is needed for the outer IPv4 checksum and\nIP and UPD tunneled packet TSO support.\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 16 ++++++++++++++++\n drivers/net/mlx5/mlx5.h | 2 ++\n drivers/net/mlx5/windows/mlx5_os.c | 6 +++++-\n drivers/net/mlx5/windows/mlx5_os.h | 6 ++++++\n 4 files changed, 29 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 45ccfe2784..add07db755 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -950,6 +950,22 @@ mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)\n \tprf->obj = NULL;\n }\n \n+uint32_t\n+mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)\n+{\n+\tuint32_t sw_parsing_offloads = 0;\n+\n+\tif (attr->swp) {\n+\t\tsw_parsing_offloads |= MLX5_SW_PARSING_CAP;\n+\t\tif (attr->swp_csum)\n+\t\t\tsw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;\n+\n+\t\tif (attr->swp_lso)\n+\t\t\tsw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;\n+\t}\n+\treturn sw_parsing_offloads;\n+}\n+\n /*\n * Allocate Rx and Tx UARs in robust fashion.\n * This routine handles the following UAR allocation issues:\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex edb4f26d42..0694927457 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1828,5 +1828,7 @@ int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh,\n \t\t\t struct rte_flow_action_conntrack *profile);\n int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,\n \t\t\t struct mlx5_aso_ct_action *ct);\n+uint32_t\n+mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr);\n \n #endif /* RTE_PMD_MLX5_H_ */\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex 26fa927039..1e258e044e 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -169,6 +169,8 @@ mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)\n \t\tdevice_attr->max_rwq_indirection_table_size =\n \t\t\t1 << hca_attr.rss_ind_tbl_cap;\n \t}\n+\tdevice_attr->sw_parsing_offloads =\n+\t\tmlx5_get_supported_sw_parsing_offloads(&hca_attr);\n \tpv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);\n \tif (pv_iseg == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to get device hca_iseg\");\n@@ -393,7 +395,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t}\n \tDRV_LOG(DEBUG, \"MPW isn't supported\");\n \tmlx5_os_get_dev_attr(sh->ctx, &device_attr);\n-\tconfig->swp = 0;\n+\tconfig->swp = device_attr.sw_parsing_offloads &\n+\t\t(MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |\n+\t\t MLX5_SW_PARSING_TSO_CAP);\n \tconfig->ind_table_max_size =\n \t\tsh->device_attr.max_rwq_indirection_table_size;\n \tcqe_comp = 0;\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h\nindex 7fe41d4e90..6de683357c 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.h\n+++ b/drivers/net/mlx5/windows/mlx5_os.h\n@@ -16,4 +16,10 @@ enum {\n \n #define MLX5_NAMESIZE MLX5_FS_NAME_MAX\n \n+enum mlx5_sw_parsing_offloads {\n+\tMLX5_SW_PARSING_CAP = 1 << 0,\n+\tMLX5_SW_PARSING_CSUM_CAP = 1 << 1,\n+\tMLX5_SW_PARSING_TSO_CAP = 1 << 2,\n+};\n+\n #endif /* RTE_PMD_MLX5_OS_H_ */\n", "prefixes": [ "03/12" ] }