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GET /api/patches/100502/?format=api
{ "id": 100502, "url": "http://patches.dpdk.org/api/patches/100502/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211005122733.12444-3-rzidane@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211005122733.12444-3-rzidane@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211005122733.12444-3-rzidane@nvidia.com", "date": "2021-10-05T12:27:30", "name": "[V6,2/5] common/mlx5: update new MMO HCA capabilities", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "da4ac59ae12d71961579a64d1a9649e0545bf140", "submitter": { "id": 2300, "url": "http://patches.dpdk.org/api/people/2300/?format=api", "name": "Raja Zidane", "email": "rzidane@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211005122733.12444-3-rzidane@nvidia.com/mbox/", "series": [ { "id": 19387, "url": "http://patches.dpdk.org/api/series/19387/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19387", "date": "2021-10-05T12:27:28", "name": "mlx5: replaced hardware queue object", "version": 6, "mbox": "http://patches.dpdk.org/series/19387/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/100502/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/100502/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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"<20211005122733.12444-1-rzidane@nvidia.com>", "References": "<20210930054438.5960-1-rzidane@nvidia.com>\n <20211005122733.12444-1-rzidane@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "6f983af7-71ce-4456-96af-08d987fb956a", "X-MS-TrafficTypeDiagnostic": "DM5PR1201MB0249:", "X-Microsoft-Antispam-PRVS": "\n <DM5PR1201MB02495936641C65CB0A5348BAC7AF9@DM5PR1201MB0249.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:1186;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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SFS:(4636009)(36840700001)(46966006)(8936002)(2616005)(8676002)(83380400001)(36756003)(6666004)(82310400003)(6916009)(70586007)(47076005)(1076003)(86362001)(356005)(7636003)(5660300002)(426003)(70206006)(7696005)(55016002)(2906002)(36860700001)(508600001)(186003)(316002)(16526019)(26005)(336012)(6286002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 Oct 2021 12:28:06.1669 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6f983af7-71ce-4456-96af-08d987fb956a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT027.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR1201MB0249", "Subject": "[dpdk-dev] [PATCH V6 2/5] common/mlx5: update new MMO HCA\n capabilities", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "New MMO HCA capabilities were added and others were renamed.\nAlign hca capabilities with new prm.\nAdd support in devx interface for changes in HCA capabilities.\n\nSigned-off-by: Raja Zidane <rzidane@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 15 ++++++++++++---\n drivers/common/mlx5/mlx5_devx_cmds.h | 11 ++++++++---\n drivers/common/mlx5/mlx5_prm.h | 20 ++++++++++++++------\n drivers/compress/mlx5/mlx5_compress.c | 4 ++--\n 4 files changed, 36 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex ac554cca05..00c78b1288 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -858,9 +858,18 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);\n \tattr->reg_c_preserve =\n \t\tMLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);\n-\tattr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);\n-\tattr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);\n-\tattr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);\n+\tattr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp);\n+\tattr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq);\n+\tattr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);\n+\tattr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\tcompress_mmo_sq);\n+\tattr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\tdecompress_mmo_sq);\n+\tattr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);\n+\tattr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\tcompress_mmo_qp);\n+\tattr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\tdecompress_mmo_qp);\n \tattr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t\t compress_min_block_size);\n \tattr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex c071629904..b21df0fd9b 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -173,9 +173,14 @@ struct mlx5_hca_attr {\n \tuint32_t log_max_srq;\n \tuint32_t log_max_srq_sz;\n \tuint32_t rss_ind_tbl_cap;\n-\tuint32_t mmo_dma_en:1;\n-\tuint32_t mmo_compress_en:1;\n-\tuint32_t mmo_decompress_en:1;\n+\tuint32_t mmo_dma_sq_en:1;\n+\tuint32_t mmo_compress_sq_en:1;\n+\tuint32_t mmo_decompress_sq_en:1;\n+\tuint32_t mmo_dma_qp_en:1;\n+\tuint32_t mmo_compress_qp_en:1;\n+\tuint32_t mmo_decompress_qp_en:1;\n+\tuint32_t mmo_regex_qp_en:1;\n+\tuint32_t mmo_regex_sq_en:1;\n \tuint32_t compress_min_block_size:4;\n \tuint32_t log_max_mmo_dma:5;\n \tuint32_t log_max_mmo_compress:5;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex d361bcf90e..ec5f871c61 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1386,10 +1386,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 rtr2rts_qp_counters_set_id[0x1];\n \tu8 rts2rts_udp_sport[0x1];\n \tu8 rts2rts_lag_tx_port_affinity[0x1];\n-\tu8 dma_mmo[0x1];\n+\tu8 dma_mmo_sq[0x1];\n \tu8 compress_min_block_size[0x4];\n-\tu8 compress[0x1];\n-\tu8 decompress[0x1];\n+\tu8 compress_mmo_sq[0x1];\n+\tu8 decompress_mmo_sq[0x1];\n \tu8 log_max_ra_res_qp[0x6];\n \tu8 end_pad[0x1];\n \tu8 cc_query_allowed[0x1];\n@@ -1519,7 +1519,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 num_lag_ports[0x4];\n \tu8 reserved_at_280[0x10];\n \tu8 max_wqe_sz_sq[0x10];\n-\tu8 reserved_at_2a0[0x10];\n+\tu8 reserved_at_2a0[0xc];\n+\tu8 regexp_mmo_sq[0x1];\n+\tu8 reserved_at_2b0[0x3];\n \tu8 max_wqe_sz_rq[0x10];\n \tu8 max_flow_counter_31_16[0x10];\n \tu8 max_wqe_sz_sq_dc[0x10];\n@@ -1632,7 +1634,12 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 num_vhca_ports[0x8];\n \tu8 reserved_at_618[0x6];\n \tu8 sw_owner_id[0x1];\n-\tu8 reserved_at_61f[0x1e1];\n+\tu8 reserved_at_61f[0x109];\n+\tu8 dma_mmo_qp[0x1];\n+\tu8 regexp_mmo_qp[0x1];\n+\tu8 compress_mmo_qp[0x1];\n+\tu8 decompress_mmo_qp[0x1];\n+\tu8 reserved_at_624[0xd4];\n };\n \n struct mlx5_ifc_qos_cap_bits {\n@@ -3244,7 +3251,8 @@ struct mlx5_ifc_create_qp_in_bits {\n \tu8 uid[0x10];\n \tu8 reserved_at_20[0x10];\n \tu8 op_mod[0x10];\n-\tu8 reserved_at_40[0x40];\n+\tu8 qpc_ext[0x1];\n+\tu8 reserved_at_41[0x3f];\n \tu8 opt_param_mask[0x20];\n \tu8 reserved_at_a0[0x20];\n \tstruct mlx5_ifc_qpc_bits qpc;\ndiff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex c5e0a83a8c..1e03030510 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -813,8 +813,8 @@ mlx5_compress_dev_probe(struct rte_device *dev)\n \t\treturn -rte_errno;\n \t}\n \tif (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 ||\n-\t att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 ||\n-\t att.mmo_dma_en == 0) {\n+\t att.mmo_compress_sq_en == 0 || att.mmo_decompress_sq_en == 0 ||\n+\t att.mmo_dma_sq_en == 0) {\n \t\tDRV_LOG(ERR, \"Not enough capabilities to support compress \"\n \t\t\t\"operations, maybe old FW/OFED version?\");\n \t\tclaim_zero(mlx5_glue->close_device(ctx));\n", "prefixes": [ "V6", "2/5" ] }