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GET /api/patches/100184/?format=api
{ "id": 100184, "url": "http://patches.dpdk.org/api/patches/100184/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210930172822.1949969-16-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210930172822.1949969-16-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210930172822.1949969-16-michaelba@nvidia.com", "date": "2021-09-30T17:28:19", "name": "[15/18] common/mlx5: share MR top-half search function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d4e5af387ff70f0464ace580c660e47236a7b28e", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210930172822.1949969-16-michaelba@nvidia.com/mbox/", "series": [ { "id": 19311, "url": "http://patches.dpdk.org/api/series/19311/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19311", "date": "2021-09-30T17:28:04", "name": "mlx5: sharing global MR cache between drivers", "version": 1, "mbox": "http://patches.dpdk.org/series/19311/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/100184/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/100184/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 91E82A0C43;\n\tThu, 30 Sep 2021 19:41:28 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1E8724116D;\n\tThu, 30 Sep 2021 19:40:02 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2067.outbound.protection.outlook.com [40.107.244.67])\n by mails.dpdk.org (Postfix) with ESMTP id 021C24067E\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=TY6PlGz++qKMNf5yXmqVi9TtwKSHpEYueL9cqFOyrJU=;\n b=SXwrbAL8Ufm1xf7E0MBfG9/eaR9G2zmqomIvdUMq7MG37lVndNzPFPugxa0lzZ68oNJ24hgn3jjlcbvlomJ0XungIf1rLgV5AwnwXynGZp54pgffPklWRfnXHvHCx60I9YaKp8/VaJyaYFuF/gNjns2pRKWsFwfLtmvgLObRDLxMHU0KN2cIm4oKvKD21Meykp0ZQAjcPKsuZeDzAvMOE+Zsxp8Tw3NKt5BgjuLz5rIMFBAlpH1uM6+0z1dFiHDg1Q0YPK5EoRTvse5B+I0BCe7d+7dRBeuwrnXlnHqtXJaqacgqIOW0kkokVYd234RoKSLTECb6Y4HwEm8HopRyLg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed)\n header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "<michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Thomas Monjalon <thomas@monjalon.net>,\n Michael Baum <michaelba@oss.nvidia.com>", "Date": "Thu, 30 Sep 2021 20:28:19 +0300", "Message-ID": "<20210930172822.1949969-16-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210930172822.1949969-1-michaelba@nvidia.com>", "References": "<20210930172822.1949969-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "b47e6cad-d001-4f24-fe05-08d98437d15f", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB3001:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB300151FBDE2D9D28D354EED0CCAA9@DM6PR12MB3001.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:3513;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n MkyC4ta3Nsm260f5mtz9PDhtnHprTOEJD8VpkPmtzdx7s1gz3RTJHKmfpgg+nIVtAFT1zez88Tzjh3ztTm2behLyvta8F0wDAKGbCxYTMJlBBHkHhqvvxKM0HUm67H38XerGbTDCijfaSsJj53DFrpLFuygQslAv43j8ra2ZYWRnJXkfphtd3C1bW9Qam3+ImqVPL14N3619hYQoYlSH22U1hVFMf9I5FDw6/Dd8uX8RugYeL74bDf7TFJxfBTj7j6OhPnUJpqidEKuGTfyvne905F3Z4DlMkmFhx2S1Uq5sq6uB9lLzwP/jiEt9UtzvjYZigTGO+/7w0RgNwllv/+fb3Pk/mfATKBXuRpmHFNL+QZecCANgPOart8kkwP3sfccJyn01N2DJZEdnTsXNHWtHG/zG+EpkeSrbgKx7catvh5YASeIP5/JkSG3Q9gAqk61iB3ikVha6p1miM0Ngq1uYjy0pC0cyGNXfxqLbtpjiEp+D5Q/5Lm3cCdLIWw+H4QKPNfuif6ZjlpaIWiI0hNjTPtk+W0aXxbjaRd1kwII3mmtAJNWmy3G8PIYVoMcmszhJnXmGGQm8PA0ri45AKlWdglyZAi/lppDPyYCSrjpG/hib1m35cakMSwBCELTfCr1BiML0ecvyDOdHQSGwDzfe8+/tCqERt5gzKwekLGAOkMaHVJSQUcuB+eqfuF9+WESgHlOPYpj54ZFS+7J75w==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(6916009)(186003)(2906002)(4326008)(8676002)(6666004)(55016002)(16526019)(47076005)(36756003)(426003)(54906003)(2616005)(86362001)(30864003)(508600001)(82310400003)(1076003)(5660300002)(83380400001)(107886003)(316002)(7696005)(356005)(36906005)(36860700001)(26005)(2876002)(336012)(70206006)(70586007)(6286002)(8936002)(7636003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Sep 2021 17:29:11.4735 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b47e6cad-d001-4f24-fe05-08d98437d15f", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT010.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB3001", "X-Mailman-Approved-At": "Thu, 30 Sep 2021 19:39:43 +0200", "Subject": "[dpdk-dev] [PATCH 15/18] common/mlx5: share MR top-half search\n function", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Michael Baum <michaelba@oss.nvidia.com>\n\nAdd function to search in local liniar cache and use it in the drivers\ninstead of their functions.\n\nSigned-off-by: Michael Baum <michaelba@oss.nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_common.h | 9 ++++\n drivers/common/mlx5/mlx5_common_mr.c | 52 ++++++++++++++++++++++++\n drivers/common/mlx5/version.map | 1 +\n drivers/compress/mlx5/mlx5_compress.c | 38 +----------------\n drivers/crypto/mlx5/mlx5_crypto.c | 38 +----------------\n drivers/regex/mlx5/mlx5_regex_fastpath.c | 34 +++++-----------\n 6 files changed, 77 insertions(+), 95 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h\nindex a863fb2b26..8df4f32aa2 100644\n--- a/drivers/common/mlx5/mlx5_common.h\n+++ b/drivers/common/mlx5/mlx5_common.h\n@@ -22,6 +22,7 @@\n #include \"mlx5_prm.h\"\n #include \"mlx5_devx_cmds.h\"\n #include \"mlx5_common_os.h\"\n+#include \"mlx5_common_mr.h\"\n \n /* Reported driver name. */\n #define MLX5_PCI_DRIVER_NAME \"mlx5_pci\"\n@@ -447,6 +448,14 @@ __rte_internal\n bool\n mlx5_dev_is_pci(const struct rte_device *dev);\n \n+/* mlx5_common_mr.c */\n+\n+__rte_internal\n+uint32_t\n+mlx5_mr_mb2mr(struct mlx5_common_device *cdev, struct mlx5_mp_id *mp_id,\n+\t struct mlx5_mr_ctrl *mr_ctrl, struct rte_mbuf *mbuf,\n+\t struct mlx5_mr_share_cache *share_cache);\n+\n /* mlx5_common_os.c */\n \n int mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes);\ndiff --git a/drivers/common/mlx5/mlx5_common_mr.c b/drivers/common/mlx5/mlx5_common_mr.c\nindex 43dc3d88ce..4de1c25f2a 100644\n--- a/drivers/common/mlx5/mlx5_common_mr.c\n+++ b/drivers/common/mlx5/mlx5_common_mr.c\n@@ -576,6 +576,8 @@ mr_find_contig_memsegs_cb(const struct rte_memseg_list *msl,\n *\n * @param pd\n * Pointer to pd of a device (net, regex, vdpa,...).\n+ * @param mp_id\n+ * Multi-process identifier, may be NULL for the primary process.\n * @param share_cache\n * Pointer to a global shared MR cache.\n * @param[out] entry\n@@ -867,6 +869,8 @@ mlx5_mr_create_primary(void *pd,\n *\n * @param pd\n * Pointer to pd handle of a device (net, regex, vdpa,...).\n+ * @param mp_id\n+ * Multi-process identifier, may be NULL for the primary process.\n * @param share_cache\n * Pointer to a global shared MR cache.\n * @param[out] entry\n@@ -874,6 +878,8 @@ mlx5_mr_create_primary(void *pd,\n * created. If failed to create one, this will not be updated.\n * @param addr\n * Target virtual address to register.\n+ * @param mr_ext_memseg_en\n+ * Configurable flag about external memory segment enable or not.\n *\n * @return\n * Searched LKey on success, UINT32_MAX on failure and rte_errno is set.\n@@ -907,6 +913,8 @@ mlx5_mr_create(void *pd, struct mlx5_mp_id *mp_id,\n *\n * @param pd\n * Pointer to pd of a device (net, regex, vdpa,...).\n+ * @param mp_id\n+ * Multi-process identifier, may be NULL for the primary process.\n * @param share_cache\n * Pointer to a global shared MR cache.\n * @param mr_ctrl\n@@ -916,6 +924,8 @@ mlx5_mr_create(void *pd, struct mlx5_mp_id *mp_id,\n * created. If failed to create one, this is not written.\n * @param addr\n * Search key.\n+ * @param mr_ext_memseg_en\n+ * Configurable flag about external memory segment enable or not.\n *\n * @return\n * Searched LKey on success, UINT32_MAX on no match.\n@@ -971,12 +981,16 @@ mr_lookup_caches(void *pd, struct mlx5_mp_id *mp_id,\n *\n * @param pd\n * Pointer to pd of a device (net, regex, vdpa,...).\n+ * @param mp_id\n+ * Multi-process identifier, may be NULL for the primary process.\n * @param share_cache\n * Pointer to a global shared MR cache.\n * @param mr_ctrl\n * Pointer to per-queue MR control structure.\n * @param addr\n * Search key.\n+ * @param mr_ext_memseg_en\n+ * Configurable flag about external memory segment enable or not.\n *\n * @return\n * Searched LKey on success, UINT32_MAX on no match.\n@@ -1822,3 +1836,41 @@ mlx5_mr_mempool2mr_bh(struct mlx5_mr_share_cache *share_cache,\n \tmr_ctrl->head = (mr_ctrl->head + 1) % MLX5_MR_CACHE_N;\n \treturn lkey;\n }\n+\n+/**\n+ * Query LKey from a packet buffer.\n+ *\n+ * @param cdev\n+ * Pointer to the mlx5 device structure.\n+ * @param mp_id\n+ * Multi-process identifier, may be NULL for the primary process.\n+ * @param mr_ctrl\n+ * Pointer to per-queue MR control structure.\n+ * @param mbuf\n+ * Pointer to mbuf.\n+ * @param share_cache\n+ * Pointer to a global shared MR cache.\n+ *\n+ * @return\n+ * Searched LKey on success, UINT32_MAX on no match.\n+ */\n+uint32_t\n+mlx5_mr_mb2mr(struct mlx5_common_device *cdev, struct mlx5_mp_id *mp_id,\n+\t struct mlx5_mr_ctrl *mr_ctrl, struct rte_mbuf *mbuf,\n+\t struct mlx5_mr_share_cache *share_cache)\n+{\n+\tuint32_t lkey;\n+\tuintptr_t addr = (uintptr_t)mbuf->buf_addr;\n+\n+\t/* Check generation bit to see if there's any change on existing MRs. */\n+\tif (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))\n+\t\tmlx5_mr_flush_local_cache(mr_ctrl);\n+\t/* Linear search on MR cache array. */\n+\tlkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,\n+\t\t\t\t MLX5_MR_CACHE_N, (uintptr_t)mbuf->buf_addr);\n+\tif (likely(lkey != UINT32_MAX))\n+\t\treturn lkey;\n+\t/* Take slower bottom-half on miss. */\n+\treturn mlx5_mr_addr2mr_bh(cdev->pd, mp_id, share_cache, mr_ctrl,\n+\t\t\t\t addr, cdev->config.mr_ext_memseg_en);\n+}\ndiff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map\nindex cabdc676d5..b83faa690c 100644\n--- a/drivers/common/mlx5/version.map\n+++ b/drivers/common/mlx5/version.map\n@@ -115,6 +115,7 @@ INTERNAL {\n \tmlx5_mr_insert_cache;\n \tmlx5_mr_lookup_cache;\n \tmlx5_mr_lookup_list;\n+\tmlx5_mr_mb2mr;\n \tmlx5_free_mr_by_addr;\n \tmlx5_mr_rebuild_cache;\n \tmlx5_mr_release_cache;\ndiff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex 6116f5113f..71c8937c47 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -431,40 +431,6 @@ static struct rte_compressdev_ops mlx5_compress_ops = {\n \t.stream_free\t\t= NULL,\n };\n \n-/**\n- * Query LKey from a packet buffer for QP. If not found, add the mempool.\n- *\n- * @param priv\n- * Pointer to the priv object.\n- * @param addr\n- * Search key.\n- * @param mr_ctrl\n- * Pointer to per-queue MR control structure.\n- * @param ol_flags\n- * Mbuf offload features.\n- *\n- * @return\n- * Searched LKey on success, UINT32_MAX on no match.\n- */\n-static __rte_always_inline uint32_t\n-mlx5_compress_addr2mr(struct mlx5_compress_priv *priv, uintptr_t addr,\n-\t\t struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags)\n-{\n-\tuint32_t lkey;\n-\n-\t/* Check generation bit to see if there's any change on existing MRs. */\n-\tif (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))\n-\t\tmlx5_mr_flush_local_cache(mr_ctrl);\n-\t/* Linear search on MR cache array. */\n-\tlkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,\n-\t\t\t\t MLX5_MR_CACHE_N, addr);\n-\tif (likely(lkey != UINT32_MAX))\n-\t\treturn lkey;\n-\t/* Take slower bottom-half on miss. */\n-\treturn mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl,\n-\t\t\t\t addr, !!(ol_flags & EXT_ATTACHED_MBUF));\n-}\n-\n static __rte_always_inline uint32_t\n mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,\n \t\t volatile struct mlx5_wqe_dseg *restrict dseg,\n@@ -474,8 +440,8 @@ mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,\n \tuintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);\n \n \tdseg->bcount = rte_cpu_to_be_32(len);\n-\tdseg->lkey = mlx5_compress_addr2mr(qp->priv, addr, &qp->mr_ctrl,\n-\t\t\t\t\t mbuf->ol_flags);\n+\tdseg->lkey = mlx5_mr_mb2mr(qp->priv->cdev, 0, &qp->mr_ctrl, mbuf,\n+\t\t\t\t &qp->priv->mr_scache);\n \tdseg->pbuf = rte_cpu_to_be_64(addr);\n \treturn dseg->lkey;\n }\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex e40c4f1e6c..0cd72822e8 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -336,40 +336,6 @@ mlx5_crypto_get_block_size(struct rte_crypto_op *op)\n \t}\n }\n \n-/**\n- * Query LKey from a packet buffer for QP. If not found, add the mempool.\n- *\n- * @param priv\n- * Pointer to the priv object.\n- * @param addr\n- * Search key.\n- * @param mr_ctrl\n- * Pointer to per-queue MR control structure.\n- * @param ol_flags\n- * Mbuf offload features.\n- *\n- * @return\n- * Searched LKey on success, UINT32_MAX on no match.\n- */\n-static __rte_always_inline uint32_t\n-mlx5_crypto_addr2mr(struct mlx5_crypto_priv *priv, uintptr_t addr,\n-\t\t struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags)\n-{\n-\tuint32_t lkey;\n-\n-\t/* Check generation bit to see if there's any change on existing MRs. */\n-\tif (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))\n-\t\tmlx5_mr_flush_local_cache(mr_ctrl);\n-\t/* Linear search on MR cache array. */\n-\tlkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,\n-\t\t\t\t MLX5_MR_CACHE_N, addr);\n-\tif (likely(lkey != UINT32_MAX))\n-\t\treturn lkey;\n-\t/* Take slower bottom-half on miss. */\n-\treturn mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl,\n-\t\t\t\t addr, !!(ol_flags & EXT_ATTACHED_MBUF));\n-}\n-\n static __rte_always_inline uint32_t\n mlx5_crypto_klm_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp,\n \t\t struct rte_mbuf *mbuf, struct mlx5_wqe_dseg *klm,\n@@ -383,8 +349,8 @@ mlx5_crypto_klm_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp,\n \t*remain -= data_len;\n \tklm->bcount = rte_cpu_to_be_32(data_len);\n \tklm->pbuf = rte_cpu_to_be_64(addr);\n-\tklm->lkey = mlx5_crypto_addr2mr(priv, addr, &qp->mr_ctrl,\n-\t\t\t\t\tmbuf->ol_flags);\n+\tklm->lkey = mlx5_mr_mb2mr(priv->cdev, 0, &qp->mr_ctrl, mbuf,\n+\t\t\t\t &priv->mr_scache);\n \treturn klm->lkey;\n \n }\ndiff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c\nindex 7a96352f52..9a7c0a6f45 100644\n--- a/drivers/regex/mlx5/mlx5_regex_fastpath.c\n+++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c\n@@ -123,26 +123,12 @@ set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode,\n * Searched LKey on success, UINT32_MAX on no match.\n */\n static inline uint32_t\n-mlx5_regex_addr2mr(struct mlx5_regex_priv *priv, struct mlx5_mr_ctrl *mr_ctrl,\n-\t\t struct rte_mbuf *mbuf)\n+mlx5_regex_mb2mr(struct mlx5_regex_priv *priv, struct mlx5_mr_ctrl *mr_ctrl,\n+\t\t struct rte_mbuf *mbuf)\n {\n-\tuintptr_t addr = rte_pktmbuf_mtod(mbuf, uintptr_t);\n-\tuint32_t lkey;\n-\n-\t/* Check generation bit to see if there's any change on existing MRs. */\n-\tif (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))\n-\t\tmlx5_mr_flush_local_cache(mr_ctrl);\n-\t/* Linear search on MR cache array. */\n-\tlkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,\n-\t\t\t\t MLX5_MR_CACHE_N, addr);\n-\tif (likely(lkey != UINT32_MAX))\n-\t\treturn lkey;\n-\t/* Take slower bottom-half on miss. */\n-\treturn mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl,\n-\t\t\t\t addr, !!(mbuf->ol_flags & EXT_ATTACHED_MBUF));\n+\treturn mlx5_mr_mb2mr(priv->cdev, 0, mr_ctrl, mbuf, &priv->mr_scache);\n }\n \n-\n static inline void\n __prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq,\n \t struct rte_regex_ops *op, struct mlx5_regex_job *job,\n@@ -194,7 +180,7 @@ prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,\n \tstruct mlx5_klm klm;\n \n \tklm.byte_count = rte_pktmbuf_data_len(op->mbuf);\n-\tklm.mkey = mlx5_regex_addr2mr(priv, &qp->mr_ctrl, op->mbuf);\n+\tklm.mkey = mlx5_regex_mb2mr(priv, &qp->mr_ctrl, op->mbuf);\n \tklm.address = rte_pktmbuf_mtod(op->mbuf, uintptr_t);\n \t__prep_one(priv, sq, op, job, sq->pi, &klm);\n \tsq->db_pi = sq->pi;\n@@ -316,6 +302,7 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,\n \tuint32_t len = 0;\n \tstruct mlx5_klm *mkey_klm = NULL;\n \tstruct mlx5_klm klm;\n+\tuintptr_t addr;\n \n \tsqid = sq->sqn;\n \twhile (left_ops--)\n@@ -360,11 +347,12 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,\n \t\t\tklm.mkey = rte_cpu_to_be_32\n \t\t\t\t\t(qp->jobs[mkey_job_id].imkey->id);\n \t\t\twhile (mbuf) {\n+\t\t\t\taddr = rte_pktmbuf_mtod(mbuf, uintptr_t);\n \t\t\t\t/* Build indirect mkey seg's KLM. */\n-\t\t\t\tmkey_klm->mkey = mlx5_regex_addr2mr\n-\t\t\t\t\t\t(priv, &qp->mr_ctrl, mbuf);\n-\t\t\t\tmkey_klm->address = rte_cpu_to_be_64\n-\t\t\t\t\t(rte_pktmbuf_mtod(mbuf, uintptr_t));\n+\t\t\t\tmkey_klm->mkey = mlx5_regex_mb2mr(priv,\n+\t\t\t\t\t\t\t\t &qp->mr_ctrl,\n+\t\t\t\t\t\t\t\t mbuf);\n+\t\t\t\tmkey_klm->address = rte_cpu_to_be_64(addr);\n \t\t\t\tmkey_klm->byte_count = rte_cpu_to_be_32\n \t\t\t\t\t\t(rte_pktmbuf_data_len(mbuf));\n \t\t\t\t/*\n@@ -380,7 +368,7 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,\n \t\t\tklm.byte_count = scatter_size;\n \t\t} else {\n \t\t\t/* The single mubf case. Build the KLM directly. */\n-\t\t\tklm.mkey = mlx5_regex_addr2mr(priv, &qp->mr_ctrl, mbuf);\n+\t\t\tklm.mkey = mlx5_regex_mb2mr(priv, &qp->mr_ctrl, mbuf);\n \t\t\tklm.address = rte_pktmbuf_mtod(mbuf, uintptr_t);\n \t\t\tklm.byte_count = rte_pktmbuf_data_len(mbuf);\n \t\t}\n", "prefixes": [ "15/18" ] }