Cover Detail
Show a cover letter.
GET /api/covers/64731/?format=api
{ "id": 64731, "url": "http://patches.dpdk.org/api/covers/64731/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/cover/20200115182832.17012-1-marcinx.smoczynski@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200115182832.17012-1-marcinx.smoczynski@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200115182832.17012-1-marcinx.smoczynski@intel.com", "date": "2020-01-15T18:28:26", "name": "[v3,0/6] Introduce CPU crypto mode", "submitter": { "id": 1293, "url": "http://patches.dpdk.org/api/people/1293/?format=api", "name": "Marcin Smoczynski", "email": "marcinx.smoczynski@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/cover/20200115182832.17012-1-marcinx.smoczynski@intel.com/mbox/", "series": [ { "id": 8142, "url": "http://patches.dpdk.org/api/series/8142/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8142", "date": "2020-01-15T18:28:26", "name": "Introduce CPU crypto mode", "version": 3, "mbox": "http://patches.dpdk.org/series/8142/mbox/" } ], "comments": "http://patches.dpdk.org/api/covers/64731/comments/", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8FEE5A0514;\n\tWed, 15 Jan 2020 19:30:24 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 68BBE1C247;\n\tWed, 15 Jan 2020 19:30:24 +0100 (CET)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by dpdk.org (Postfix) with ESMTP id 18B271C246\n for <dev@dpdk.org>; Wed, 15 Jan 2020 19:30:22 +0100 (CET)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 15 Jan 2020 10:30:22 -0800", "from msmoczyx-mobl.ger.corp.intel.com ([10.104.125.3])\n by fmsmga001.fm.intel.com with ESMTP; 15 Jan 2020 10:30:20 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,323,1574150400\"; d=\"scan'208\";a=\"254502145\"", "From": "Marcin Smoczynski <marcinx.smoczynski@intel.com>", "To": "akhil.goyal@nxp.com, konstantin.ananyev@intel.com,\n roy.fan.zhang@intel.com,\n declan.doherty@intel.com, radu.nicolau@intel.com", "Cc": "dev@dpdk.org,\n\tMarcin Smoczynski <marcinx.smoczynski@intel.com>", "Date": "Wed, 15 Jan 2020 19:28:26 +0100", "Message-Id": "<20200115182832.17012-1-marcinx.smoczynski@intel.com>", "X-Mailer": "git-send-email 2.21.0.windows.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 0/6] Introduce CPU crypto mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Originally both SW and HW crypto PMDs use rte_crypot_op based API to\nprocess the crypto workload asynchronously. This way provides uniformity\nto both PMD types, but also introduce unnecessary performance penalty to\nSW PMDs that have to \"simulate\" HW async behavior (crypto-ops\nenqueue/dequeue, HW addresses computations, storing/dereferencing user\nprovided data (mbuf) for each crypto-op, etc).\n\nThe aim is to introduce a new optional API for SW crypto-devices\nto perform crypto processing in a synchronous manner.\n\nMarcin Smoczynski (6):\n cryptodev: introduce cpu crypto support API\n crypto/aesni_gcm: cpu crypto support\n security: add cpu crypto action type\n ipsec: introduce support for cpu crypto mode\n examples/ipsec-secgw: cpu crypto support\n examples/ipsec-secgw: cpu crypto testing\n\n drivers/crypto/aesni_gcm/aesni_gcm_ops.h | 9 +\n drivers/crypto/aesni_gcm/aesni_gcm_pmd.c | 149 ++++++++++++++++-\n drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c | 3 +\n .../crypto/aesni_gcm/aesni_gcm_pmd_private.h | 18 +-\n examples/ipsec-secgw/ipsec.c | 12 +-\n examples/ipsec-secgw/ipsec_process.c | 134 +++++++++------\n examples/ipsec-secgw/sa.c | 33 +++-\n examples/ipsec-secgw/test/common_defs.sh | 21 +++\n examples/ipsec-secgw/test/linux_test4.sh | 11 +-\n examples/ipsec-secgw/test/linux_test6.sh | 11 +-\n .../test/trs_3descbc_sha1_common_defs.sh | 8 +-\n .../test/trs_aescbc_sha1_common_defs.sh | 8 +-\n .../test/trs_aesctr_sha1_common_defs.sh | 8 +-\n .../test/tun_3descbc_sha1_common_defs.sh | 8 +-\n .../test/tun_aescbc_sha1_common_defs.sh | 8 +-\n .../test/tun_aesctr_sha1_common_defs.sh | 8 +-\n lib/librte_cryptodev/rte_crypto_sym.h | 62 ++++++-\n lib/librte_cryptodev/rte_cryptodev.c | 30 ++++\n lib/librte_cryptodev/rte_cryptodev.h | 20 +++\n lib/librte_cryptodev/rte_cryptodev_pmd.h | 19 +++\n .../rte_cryptodev_version.map | 1 +\n lib/librte_ipsec/esp_inb.c | 154 +++++++++++++++---\n lib/librte_ipsec/esp_outb.c | 134 +++++++++++++--\n lib/librte_ipsec/misc.h | 118 ++++++++++++++\n lib/librte_ipsec/rte_ipsec.h | 18 +-\n lib/librte_ipsec/sa.c | 126 +++++++++++---\n lib/librte_ipsec/sa.h | 17 ++\n lib/librte_ipsec/ses.c | 3 +-\n lib/librte_security/rte_security.h | 6 +-\n 29 files changed, 990 insertions(+), 167 deletions(-)" }