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{ "id": 588, "url": "http://patches.dpdk.org/api/covers/588/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/cover/20240125133043.575860-1-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240125133043.575860-1-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240125133043.575860-1-michaelba@nvidia.com", "date": "2024-01-25T13:30:20", "name": "[v2,00/23] net/mlx5: support Geneve and options for HWS", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/cover/20240125133043.575860-1-michaelba@nvidia.com/mbox/", "series": [ { "id": 30916, "url": "http://patches.dpdk.org/api/series/30916/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30916", "date": "2024-01-25T13:30:20", "name": "net/mlx5: support Geneve and options for HWS", "version": 2, "mbox": "http://patches.dpdk.org/series/30916/mbox/" } ], "comments": "http://patches.dpdk.org/api/covers/588/comments/", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 43A62439C1;\n\tThu, 25 Jan 2024 14:31:04 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B5E69402AB;\n\tThu, 25 Jan 2024 14:31:03 +0100 (CET)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2089.outbound.protection.outlook.com [40.107.220.89])\n by mails.dpdk.org (Postfix) with ESMTP id D656D4029B\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "Subject": "[PATCH v2 00/23] net/mlx5: support Geneve and options for HWS", "Date": "Thu, 25 Jan 2024 15:30:20 +0200", "Message-ID": "<20240125133043.575860-1-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231203112543.844014-1-michaelba@nvidia.com>", "References": "<20231203112543.844014-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EDD0:EE_|DM4PR12MB6061:EE_", "X-MS-Office365-Filtering-Correlation-Id": "ee3c3edd-5de7-48b1-d28d-08dc1da9dd9e", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n nj+/WE7p8zAhae6a0EPTZb7jYYJhOSuKyPX5Cg22ttN3v8QJHiO9juwwX5i93wm+/PZkryecglgHkIUnscujhIhilG0DVM83Y/qozDb+RkvtDvHnbhAEkI+amyTUfgxT2+VTPRQ8mFjy/tkjftCKIc6tj9a+D4IbCjkK+0+gMAI8JkBQTkfzt1qOgJVxy4pK/MCULV8kLQW8MkaQvMPm2DKTBff0cGQQZLaoOzxUFvC6EFA6mcdmSVcI+Yk6kWdbySEQtEv/yfMt0bAU85E4dNNXtovrBJ6fN9D97uFdz3LsoFm0HQkf75C+mLaXedQvoZ88zeWmwzdmqwm94D7GBer41A7DZ+i32zJLirb718WRV+YAeksIEmLM0hEIeKJpWyEmtiG7dXV/z12NYGNOXtys2kaEQJ8h2pXU0eELZsxLZt7pqmdIIqcusYtGXZMxhTSu/GjWTHNjJ1Zl8lOobVsJrH8anhmW4sThxXtN1e2VmHK3Ce7eDeop2rQmFL4qiG/jPwSoBao/jzLjLbtssUcsf4HOPNm7SfcHlKvaBDxg5Dvy37V9R4rk/vu+ouGpT0Ex9Mt0QgFO9lyOJKY2VYdUWtORkf4bz/JgqWadQ+hRIrSBpoh4paba2U3WabYpJtz2K4d9Lq167/ILSx1sQua1FQdbRDAKyAGyuSXvq1vTrkFwwFV4LzDya38arAfvDT15drml3O0aKLi2nGFvW3hiqr1BEFbe+3W7nl9jqYNHUXNsAdeT716XyZzB5JDj", "X-Forefront-Antispam-Report": "CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(39860400002)(376002)(346002)(136003)(396003)(230922051799003)(451199024)(1800799012)(82310400011)(64100799003)(186009)(40470700004)(36840700001)(46966006)(478600001)(55016003)(40460700003)(40480700001)(6666004)(1076003)(6286002)(82740400003)(4326008)(5660300002)(8676002)(426003)(336012)(2906002)(83380400001)(36860700001)(7696005)(8936002)(7636003)(47076005)(26005)(54906003)(70586007)(41300700001)(86362001)(6916009)(36756003)(2616005)(70206006)(107886003)(316002)(356005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Jan 2024 13:30:58.3525 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ee3c3edd-5de7-48b1-d28d-08dc1da9dd9e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EDD0.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB6061", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add HWS support for both GENEVE and GENEVE TLV option headers.\nThis patchset supports:\n\n - Add HW support for \"RTE_FLOW_ITEM_TYPE_GENEVE\" flow item.\n - Add HW support for \"RTE_FLOW_ITEM_TYPE_GENEVE_OPT\" flow item.\n - Add HW support for \"RTE_FLOW_FIELD_GENEVE_VNI\" for modify field flow\n action.\n - Add HW support for \"RTE_FLOW_FIELD_GENEVE_OPT_TYPE\" for modify field\n flow action.\n - Add HW support for \"RTE_FLOW_FIELD_GENEVE_OPT_CLASS\" for modify field\n flow action.\n - Add HW support for \"RTE_FLOW_FIELD_GENEVE_OPT_DATA\" for modify field\n flow action.\n\nThe GENEVE TLV options support using flex parser.\nThe profile should be specified to either 8 for multiple option or 0 for\nsingle option.\nA new API is added to create the GENEVE option parser before using it in\ntemplates API.\n\nv2:\n - Rebase.\n - Add \"Acked-by\" from v1.\n\nAlex Vesker (4):\n net/mlx5/hws: fix tunnel protocol checks\n net/mlx5/hws: increase hl size for future compatibility\n net/mlx5/hws: support GENEVE matching\n net/mlx5/hws: support GENEVE options header\n\nMichael Baum (19):\n common/mlx5: fix duplicate read of general capabilities\n common/mlx5: fix query sample info capability\n net/mlx5: remove GENEVE options length limitation\n net/mlx5: fix GENEVE option item translation\n common/mlx5: add system image GUID attribute\n common/mlx5: add GENEVE TLV option attribute structure\n common/mlx5: add PRM attribute for TLV sample\n common/mlx5: add sample info query syndrome into error log\n common/mlx5: query GENEVE option sample ID from HCA attr\n common/mlx5: add function to query GENEVE TLV option\n net/mlx5: add physical device handle\n net/mlx5: add GENEVE TLV options parser API\n net/mlx5: add API to expose GENEVE option FW information\n net/mlx5: add testpmd support for GENEVE TLV parser\n net/mlx5: add support for GENEVE and option item in HWS\n net/mlx5: add GENEVE option support for profile 0\n net/mlx5: add GENEVE option support for group 0\n net/mlx5: add support for GENEVE VNI modify field\n net/mlx5: add support for modify GENEVE option header\n\n doc/guides/nics/mlx5.rst | 251 +++++-\n doc/guides/platform/mlx5.rst | 2 +\n doc/guides/rel_notes/release_24_03.rst | 9 +\n drivers/common/mlx5/mlx5_devx_cmds.c | 139 +++-\n drivers/common/mlx5/mlx5_devx_cmds.h | 29 +-\n drivers/common/mlx5/mlx5_prm.h | 20 +-\n drivers/common/mlx5/version.map | 1 +\n drivers/net/mlx5/hws/mlx5dr_definer.c | 281 ++++++-\n drivers/net/mlx5/hws/mlx5dr_definer.h | 49 +-\n drivers/net/mlx5/meson.build | 1 +\n drivers/net/mlx5/mlx5.c | 115 ++-\n drivers/net/mlx5/mlx5.h | 21 +\n drivers/net/mlx5/mlx5_flow.c | 30 +\n drivers/net/mlx5/mlx5_flow.h | 92 ++-\n drivers/net/mlx5/mlx5_flow_dv.c | 158 ++--\n drivers/net/mlx5/mlx5_flow_geneve.c | 1011 ++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow_hw.c | 127 ++-\n drivers/net/mlx5/mlx5_testpmd.c | 556 ++++++++++++-\n drivers/net/mlx5/rte_pmd_mlx5.h | 102 +++\n drivers/net/mlx5/version.map | 3 +\n 20 files changed, 2811 insertions(+), 186 deletions(-)\n create mode 100644 drivers/net/mlx5/mlx5_flow_geneve.c" }