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[
    {
        "id": 95942,
        "web_url": "http://patches.dpdk.org/comment/95942/",
        "msgid": "<2715295a-43fa-cc8b-8271-ded8b237501a@kth.se>",
        "date": "2019-05-08T07:49:59",
        "subject": "Re: [dpdk-dev] [PATCH v4 0/3] Add rte_eth_read_clock API",
        "submitter": {
            "id": 1155,
            "url": "http://patches.dpdk.org/api/people/1155/",
            "name": "Tom Barbette",
            "email": "barbette@kth.se"
        },
        "content": "Maybe a (last) motivation point.\n\nWe just did a 100G link traffic capture with time-stamping of all \npackets in HW using a Mellanox CX5. SW time-stamping fails to reveal \nqueueing delays, and as multi-queue is needed for writing 100G traffic \nto multiple NVMe drives, does not allow to recover the original ordering \nmixed by multi-queuing.\n\nHere, we timestamped traffic in hardware (FYI, given in ticks of the \ninternal CX5 clock, not in unit of time), and thanks to the new API, \nconverted it to real time value (through frequency + base).\n\nBut precision is not the only improvement. As DPDK is userlevel, calling \nget_timeofday for millions of packets pretty much kills the capture.\nHere we do a simple math per packet to convert the packet's timestamp in \nticks to the real clock time, (very) much cheaper than even a vDSO syscall.\n\nTom\n\n\nOn 2019-05-02 14:11, Tom Barbette wrote:\n> Some NICs allow to timestamp packets, but do not support the full\n> PTP synchronization process. Hence, the value set in the mbuf\n> timestamp field is only the raw value of an internal clock.\n> \n> To make sense of this value, one at least needs to be able to query\n> the current hardware clock value. This patch series adds a new API to do\n> so, rte_eth_read_clock. As with the TSC, from there\n> a frequency can be derieved by querying multiple time the current value of the\n> internal clock with some known delay between the queries (example\n> provided in the API doc).\n> \n> This patch series adds support of read_clock for MLX5.\n> \n> An example app is provided in the rxtx_callback application.\n> It has been updated to display, on top of the software latency\n> in cycles, the total latency since the packet was received in hardware.\n> The API is used to compute a delta in the Tx callback. The raw amount of\n> ticks is converted to cycles using a variation of the technique describe above.\n> \n> Aside from offloading timestamping, which relieve the\n> software from a few operations, this allows to get much more precision\n> when studying the source of the latency in a system.\n> Eg. in our 100G, CX5 setup the rxtx callback application shows\n> SW latency is around 74 cycles (TSC is 3.2Ghz), but the latency\n> including NIC processing, PCIe, and queuing is around 196 cycles.\n> \n> One may think at first this API is overlapping with te_eth_timesync_read_time.\n> rte_eth_timesync_read_time is clearly identified as part of a set of functions\n> to use PTP synchronization.\n> The device raw clock is not \"sync\" in any way. More importantly, the returned\n> value is not a timeval, but an amount of ticks. We could have a cast-based\n> solution, but on top of being an ugly solution, some people seeing the timeval\n> type of rte_eth_timesync_read_time could use it blindly.\n> \n> Change in v2:\n>    - Rebase on current master\n> \n> Change in v3:\n>    - Address comments from Ferruh Yigit\n> \n> Changes in v4:\n>    - Address comments from Keith Wiles and Andrew Rybchenko\n>    - Use \"clock\" as argunment name everywhere.\n>    - Expand the API description to make clear that read_clock gives an\n>      amount in ticks, and that it has no unit.\n> \n> Tom Barbette (3):\n>    rte_ethdev: Add API function to read dev clock\n>    mlx5: Implement support for read_clock\n>    rxtx_callbacks: Add support for HW timestamp\n> \n>   doc/guides/nics/features.rst                |  1 +\n>   doc/guides/sample_app_ug/rxtx_callbacks.rst |  9 ++-\n>   drivers/net/mlx5/mlx5.c                     |  1 +\n>   drivers/net/mlx5/mlx5.h                     |  1 +\n>   drivers/net/mlx5/mlx5_ethdev.c              | 30 +++++++\n>   drivers/net/mlx5/mlx5_glue.c                |  8 ++\n>   drivers/net/mlx5/mlx5_glue.h                |  2 +\n>   examples/rxtx_callbacks/Makefile            |  3 +\n>   examples/rxtx_callbacks/main.c              | 87 ++++++++++++++++++++-\n>   examples/rxtx_callbacks/meson.build         |  3 +\n>   lib/librte_ethdev/rte_ethdev.c              | 12 +++\n>   lib/librte_ethdev/rte_ethdev.h              | 47 +++++++++++\n>   lib/librte_ethdev/rte_ethdev_core.h         |  6 ++\n>   lib/librte_ethdev/rte_ethdev_version.map    |  1 +\n>   lib/librte_mbuf/rte_mbuf.h                  |  2 +\n>   15 files changed, 208 insertions(+), 5 deletions(-)\n>",
        "headers": {
            "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
            "From": "Tom Barbette <barbette@kth.se>",
            "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
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            "Cc": "bruce.richardson@intel.com, john.mcnamara@intel.com,\n\tThomas Monjalon <thomas@monjalon.net>, Ferruh Yigit\n\t<ferruh.yigit@intel.com>, Andrew Rybchenko <arybchenko@solarflare.com>,\n\tShahaf Shuler <shahafs@mellanox.com>, Yongseok Koh <yskoh@mellanox.com>, \n\tolivier.matz@6wind.com",
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            "Date": "Wed, 8 May 2019 09:49:59 +0200",
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            "Content-Type": "text/plain; charset=utf-8; format=flowed",
            "Subject": "Re: [dpdk-dev] [PATCH v4 0/3] Add rte_eth_read_clock API",
            "In-Reply-To": "<20190502121135.18775-1-barbette@kth.se>",
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    },
    {
        "id": 96579,
        "web_url": "http://patches.dpdk.org/comment/96579/",
        "msgid": "<06a590d0-e0bf-53d2-7b40-94f55ea1f141@intel.com>",
        "date": "2019-05-31T07:46:27",
        "subject": "Re: [dpdk-dev] [PATCH v4 0/3] Add rte_eth_read_clock API",
        "submitter": {
            "id": 324,
            "url": "http://patches.dpdk.org/api/people/324/",
            "name": "Ferruh Yigit",
            "email": "ferruh.yigit@intel.com"
        },
        "content": "On 5/2/2019 1:11 PM, Tom Barbette wrote:\n> Some NICs allow to timestamp packets, but do not support the full\n> PTP synchronization process. Hence, the value set in the mbuf\n> timestamp field is only the raw value of an internal clock.\n> \n> To make sense of this value, one at least needs to be able to query\n> the current hardware clock value. This patch series adds a new API to do\n> so, rte_eth_read_clock. As with the TSC, from there\n> a frequency can be derieved by querying multiple time the current value of the\n> internal clock with some known delay between the queries (example\n> provided in the API doc).\n> \n> This patch series adds support of read_clock for MLX5.\n> \n> An example app is provided in the rxtx_callback application.\n> It has been updated to display, on top of the software latency\n> in cycles, the total latency since the packet was received in hardware.\n> The API is used to compute a delta in the Tx callback. The raw amount of\n> ticks is converted to cycles using a variation of the technique describe above.\n> \n> Aside from offloading timestamping, which relieve the\n> software from a few operations, this allows to get much more precision\n> when studying the source of the latency in a system.\n> Eg. in our 100G, CX5 setup the rxtx callback application shows\n> SW latency is around 74 cycles (TSC is 3.2Ghz), but the latency\n> including NIC processing, PCIe, and queuing is around 196 cycles.\n> \n> One may think at first this API is overlapping with te_eth_timesync_read_time.\n> rte_eth_timesync_read_time is clearly identified as part of a set of functions\n> to use PTP synchronization.\n> The device raw clock is not \"sync\" in any way. More importantly, the returned\n> value is not a timeval, but an amount of ticks. We could have a cast-based\n> solution, but on top of being an ugly solution, some people seeing the timeval\n> type of rte_eth_timesync_read_time could use it blindly.\n> \n> Change in v2:\n>   - Rebase on current master\n> \n> Change in v3:\n>   - Address comments from Ferruh Yigit\n> \n> Changes in v4:\n>   - Address comments from Keith Wiles and Andrew Rybchenko\n>   - Use \"clock\" as argunment name everywhere.\n>   - Expand the API description to make clear that read_clock gives an\n>     amount in ticks, and that it has no unit.\n> \n> Tom Barbette (3):\n>   rte_ethdev: Add API function to read dev clock\n>   mlx5: Implement support for read_clock\n>   rxtx_callbacks: Add support for HW timestamp\n\nSeries applied to dpdk-next-net/master, thanks.",
        "headers": {
            "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
            "From": "Ferruh Yigit <ferruh.yigit@intel.com>",
            "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
            "Date": "Fri, 31 May 2019 08:46:27 +0100",
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            "Cc": "bruce.richardson@intel.com, john.mcnamara@intel.com,\n\tThomas Monjalon <thomas@monjalon.net>,\n\tAndrew Rybchenko <arybchenko@solarflare.com>,\n\tShahaf Shuler <shahafs@mellanox.com>, Yongseok Koh <yskoh@mellanox.com>, \n\tolivier.matz@6wind.com",
            "To": "Tom Barbette <barbette@kth.se>, dev@dpdk.org",
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            "Subject": "Re: [dpdk-dev] [PATCH v4 0/3] Add rte_eth_read_clock API",
            "In-Reply-To": "<20190502121135.18775-1-barbette@kth.se>",
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