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{
    "id": 52221,
    "url": "http://patches.dpdk.org/api/covers/52221/?format=api",
    "web_url": "http://patches.dpdk.org/cover/52221/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20190403173438.23691-1-gage.eads@intel.com>",
    "date": "2019-04-03T17:34:37",
    "name": "[v4,0/1] Add 128-bit compare and set",
    "submitter": {
        "id": 586,
        "url": "http://patches.dpdk.org/api/people/586/?format=api",
        "name": "Eads, Gage",
        "email": "gage.eads@intel.com"
    },
    "mbox": "http://patches.dpdk.org/cover/52221/mbox/",
    "series": [
        {
            "id": 4097,
            "url": "http://patches.dpdk.org/api/series/4097/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4097",
            "date": "2019-04-03T17:34:37",
            "name": "Add 128-bit compare and set",
            "version": 4,
            "mbox": "http://patches.dpdk.org/series/4097/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/covers/52221/comments/",
    "headers": {
        "X-Mailer": "git-send-email 2.13.6",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "Precedence": "list",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Date": "Wed,  3 Apr 2019 12:34:37 -0500",
        "X-Mailman-Version": "2.1.15",
        "Delivered-To": "patchwork@dpdk.org",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "Cc": "olivier.matz@6wind.com, arybchenko@solarflare.com,\n\tbruce.richardson@intel.com, konstantin.ananyev@intel.com,\n\tgavin.hu@arm.com, \n\tHonnappa.Nagarahalli@arm.com, nd@arm.com, chaozhu@linux.vnet.ibm.com, \n\tjerinj@marvell.com, hemant.agrawal@nxp.com, thomas@monjalon.net",
        "To": "dev@dpdk.org",
        "Errors-To": "dev-bounces@dpdk.org",
        "References": "<20190304205133.2248-1-gage.eads@intel.com>",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "Gage Eads <gage.eads@intel.com>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-IronPort-AV": "E=Sophos;i=\"5.60,305,1549958400\"; d=\"scan'208\";a=\"334697325\"",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F2A831B513;\n\tWed,  3 Apr 2019 19:35:32 +0200 (CEST)",
            "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id 33F691B4E5\n\tfor <dev@dpdk.org>; Wed,  3 Apr 2019 19:35:31 +0200 (CEST)",
            "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t03 Apr 2019 10:35:30 -0700",
            "from txasoft-yocto.an.intel.com ([10.123.72.192])\n\tby fmsmga005.fm.intel.com with ESMTP; 03 Apr 2019 10:35:29 -0700"
        ],
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "X-Amp-File-Uploaded": "False",
        "Subject": "[dpdk-dev] [PATCH v4 0/1] Add 128-bit compare and set",
        "In-Reply-To": "<20190304205133.2248-1-gage.eads@intel.com>",
        "Message-Id": "<20190403173438.23691-1-gage.eads@intel.com>",
        "X-ExtLoop1": "1",
        "X-BeenThere": "dev@dpdk.org",
        "X-Original-To": "patchwork@dpdk.org"
    },
    "content": "This patch addresses x86-64 only; other architectures can/will be supported\nin the future. The __atomic intrinsic was considered for the implementation,\nhowever libatomic was found[1] to use locks to implement the 128-bit CAS on at\nleast one architecture and so is eschewed here. The interface is modeled after\nthe __atomic_compare_exchange_16 (which itself is based on the C++11 memory\nmodel) to best support weak consistency architectures.\n\nThis patch was originally part of a series that introduces a non-blocking stack\nmempool handler[2], and is required by a non-blocking ring patchset. This\npatch was spun off so that the the NB ring depends only on this patch\nand not on the entire non-blocking stack patchset.\n\n[1] http://mails.dpdk.org/archives/dev/2019-January/124002.html\n[2] http://mails.dpdk.org/archives/dev/2019-January/123653.html\n\nv4:\n - Move function declaration from generic/rte_atomic.h to x86-64 header file\n\nv3:\n - Rename function to ISA-neutral rte_atomic128_cmp_exchange()\n - Fix two pseudocode bugs in function documentation\n\nv2:\n - Rename function to rte_atomic128_cmpxchg()\n - Replace \"=A\" output constraint with \"=a\" and \"=d\" to prevent GCC from using\n   the al register for the sete destination\n - Extend 'weak' definition to allow non-atomic 'exp' updates.\n - Add const keyword to 'src' and remove volatile keyword from 'dst'\n - Put __int128 in a union in rte_int128_t and move the structure definition\n   inside the RTE_ARCH_x86_64 ifdef\n - Drop enum rte_atomic_memmodel_t in favor of compiler-defined __ATOMIC_*\n - Drop unnecessary comment relating to X86_64\n - Tweak the pseudocode to reflect the 'exp' update on failure.\n\nGage Eads (1):\n  eal: add 128-bit compare exchange (x86-64 only)\n\n .../common/include/arch/x86/rte_atomic_64.h        | 81 ++++++++++++++++++++++\n 1 file changed, 81 insertions(+)"
}