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    "id": 52221,
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    "msgid": "<>",
    "date": "2019-04-03T17:34:37",
    "name": "[v4,0/1] Add 128-bit compare and set",
    "submitter": {
        "id": 586,
        "url": "",
        "name": "Eads, Gage",
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            "date": "2019-04-03T17:34:37",
            "name": "Add 128-bit compare and set",
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    "headers": {
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        "List-Id": "DPDK patches and discussions <>",
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        "Date": "Wed,  3 Apr 2019 12:34:37 -0500",
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        "From": "Gage Eads <>",
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        "Subject": "[dpdk-dev] [PATCH v4 0/1] Add 128-bit compare and set",
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    "content": "This patch addresses x86-64 only; other architectures can/will be supported\nin the future. The __atomic intrinsic was considered for the implementation,\nhowever libatomic was found[1] to use locks to implement the 128-bit CAS on at\nleast one architecture and so is eschewed here. The interface is modeled after\nthe __atomic_compare_exchange_16 (which itself is based on the C++11 memory\nmodel) to best support weak consistency architectures.\n\nThis patch was originally part of a series that introduces a non-blocking stack\nmempool handler[2], and is required by a non-blocking ring patchset. This\npatch was spun off so that the the NB ring depends only on this patch\nand not on the entire non-blocking stack patchset.\n\n[1]\n[2]\n\nv4:\n - Move function declaration from generic/rte_atomic.h to x86-64 header file\n\nv3:\n - Rename function to ISA-neutral rte_atomic128_cmp_exchange()\n - Fix two pseudocode bugs in function documentation\n\nv2:\n - Rename function to rte_atomic128_cmpxchg()\n - Replace \"=A\" output constraint with \"=a\" and \"=d\" to prevent GCC from using\n   the al register for the sete destination\n - Extend 'weak' definition to allow non-atomic 'exp' updates.\n - Add const keyword to 'src' and remove volatile keyword from 'dst'\n - Put __int128 in a union in rte_int128_t and move the structure definition\n   inside the RTE_ARCH_x86_64 ifdef\n - Drop enum rte_atomic_memmodel_t in favor of compiler-defined __ATOMIC_*\n - Drop unnecessary comment relating to X86_64\n - Tweak the pseudocode to reflect the 'exp' update on failure.\n\nGage Eads (1):\n  eal: add 128-bit compare exchange (x86-64 only)\n\n .../common/include/arch/x86/rte_atomic_64.h        | 81 ++++++++++++++++++++++\n 1 file changed, 81 insertions(+)"