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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH v3 00/14] net/mlx5: add hardware steering", "Date": "Thu, 24 Feb 2022 05:10:15 +0200", "Message-ID": "<20220224031029.14049-1-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220210162926.20436-1-suanmingm@nvidia.com>", "References": "<20220210162926.20436-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "a4bed7eb-be7d-4234-3cdb-08d9f7435232", "X-MS-TrafficTypeDiagnostic": "BL0PR12MB2466:EE_", "X-Microsoft-Antispam-PRVS": "\n <BL0PR12MB2466326EFEC5EBB4AE187650C13D9@BL0PR12MB2466.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Jc7b4s0GDA9eV4iA3SE//gksaiiXvtXvtEWcU3uzxbE/etkXSpJGuSYGZRsNRIuhE/aLxjWMx1OJV2mxVcOoGXcFXVPhiU0Yswr8HgMvpnLC0XkJber9e4+Jmb/MgUJrcGMxJSwaFFInQSKTZXbOBnukxD0nTFe/gP4yNL+8rnOZ1OwHCZGxtwBom3dQRaYhzfkG8J3tI4n7NRxOHIecDTg59bFcx1NqbFkF0wclTb9k6tDbift1uqtFBkd+lnJmtswAxvOswPr7o4KG4sKHvJ/QzpETAMBEojm9K/v6Pbl1R+mm8xoQ55qEMF66PS3lERN8TtNeue/If25BYurxaMhNERV3Hu313EC73u5Iuqbd1DR2Arpp9VpxUVxeU2GBzaYxIsOhAZdbl+IA7s2Tqovk4hBsnlpw/wyT1OFZOWd4lfOZEbRsVv78gbGbgoTn3zx5T7/5zp4FvqeIlqIPdOnH7cblpxpZaACDK3BekzUYGinIqY8Z0LBeOSqFiegFRVHS3J1pQJKY9HeCzKk6nzefhH5GKN4lboXgUNaAhzFXHI6aF4ogf7mw3T/hz6hcd60CwHeCdmkx4KV2oecG/lpi/8vYAzR+xMItgVWwoDpA1MJjQ/fIjnJ70gGu0il3QuWxfevI5SBYlZ3PgVhDj0fk9dVwAn6z5JnXbRKZ4nYgdsNswNpATjgXgugZ2HmtzI80cZI12ZSzYKQifjkLrA==", "X-Forefront-Antispam-Report": "CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(70206006)(70586007)(40460700003)(1076003)(8936002)(4326008)(16526019)(6286002)(186003)(86362001)(82310400004)(47076005)(83380400001)(8676002)(316002)(54906003)(5660300002)(6636002)(110136005)(2616005)(26005)(508600001)(336012)(426003)(36860700001)(7696005)(81166007)(55016003)(6666004)(356005)(36756003)(2906002)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Feb 2022 03:11:16.2279 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a4bed7eb-be7d-4234-3cdb-08d9f7435232", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT066.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL0PR12MB2466", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The Connect-X steering is a lookup hardware mechanism that accesses\nflow tables, matches packets to the rules, and performs specified actions.\nHistorically, mlx5 PMD implements several software engines to manage\nsteering hardware facility:\n\n - FW Steering - Verbs/Direct Verbs, uses FW calls to manage flows\n - SW Steering - DevX/mlx5dv, uses WQEs to access table memory directly\n\nHowever, there are still some disadvantages:\n\n - performance is limited, we should invoke firmware either to\n manage the entire flow, or to handle some internal steering objects\n\n - organizing and preparing flow infrastructure (actions, matchers,\n groups, etc.) on the flow inserting is sure to cause slow flow\n insertion\n\n - security, exposing the low-level steering entries directly to the\n userspace may cause security risks\n\nA new hardware WQE based steering operation with codename \"HW Steering\"\nis going to be introduced to get rid of the security risks. And it will\ntake advantage of the recently new introduced async queue-based rte_flow\nAPIs to prepare everything in advance to achieve high insertion rate.\n\nIn this new HW steering engine, the original SW steering rte_flow API\nwill not be supported in the first implementation, only the new async\nqueue-based flow operations is going to be supported. A new steering\nmode parameter for dv_flow_en will be introduced and user will be\nable to engage the new steering engine.\n\n*** THIS PATCH SET DEPENDS ON THE NEW RTE_FLOW ASYNC API ***\n\n---\n\nv3:\n - rebase to the latest version.\n\nv2:\n - New HW steering low-level abstract code added.\n - commit message improvement.\n - add protection for rte_flow and rte_flow_async callbacks.\n - rebase to rte_flow_async v9.\n - fix some rte_flow error not filled bugs.\n\n\nSuanming Mou (14):\n net/mlx5: introduce hardware steering operation\n net/mlx5: add HW steering low-level abstract code\n net/mlx5: introduce hardware steering enable routine\n net/mlx5: add port flow configuration\n net/mlx5: add pattern template management\n net/mlx5: add action template management\n net/mlx5: add table management\n net/mlx5: add basic flow queue operation\n net/mlx5: add flow flush function\n net/mlx5: add flow jump action\n net/mlx5: add queue and RSS action\n net/mlx5: add mark action\n net/mlx5: add indirect action\n net/mlx5: add header reformat action\n\n doc/guides/nics/mlx5.rst | 19 +-\n doc/guides/rel_notes/release_22_03.rst | 6 +\n drivers/net/mlx5/linux/mlx5_flow_os.h | 1 +\n drivers/net/mlx5/linux/mlx5_os.c | 22 +-\n drivers/net/mlx5/meson.build | 2 +\n drivers/net/mlx5/mlx5.c | 55 +-\n drivers/net/mlx5/mlx5.h | 66 +-\n drivers/net/mlx5/mlx5_devx.c | 10 +\n drivers/net/mlx5/mlx5_dr.c | 383 ++++\n drivers/net/mlx5/mlx5_dr.h | 456 +++++\n drivers/net/mlx5/mlx5_flow.c | 721 ++++++-\n drivers/net/mlx5/mlx5_flow.h | 287 +++\n drivers/net/mlx5/mlx5_flow_dv.c | 186 +-\n drivers/net/mlx5/mlx5_flow_hw.c | 2335 +++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow_verbs.c | 7 +-\n drivers/net/mlx5/mlx5_rx.h | 9 +-\n drivers/net/mlx5/mlx5_rxq.c | 85 +-\n drivers/net/mlx5/windows/mlx5_flow_os.h | 1 +\n 18 files changed, 4471 insertions(+), 180 deletions(-)\n create mode 100644 drivers/net/mlx5/mlx5_dr.c\n create mode 100644 drivers/net/mlx5/mlx5_dr.h\n create mode 100644 drivers/net/mlx5/mlx5_flow_hw.c" }