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{ "id": 107311, "url": "http://patches.dpdk.org/api/covers/107311/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/cover/20220211014530.77711-1-xiazhang@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220211014530.77711-1-xiazhang@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220211014530.77711-1-xiazhang@nvidia.com", "date": "2022-02-11T01:45:26", "name": "[v2,0/4] Add support for GRE optional fields matching", "submitter": { "id": 2383, "url": "http://patches.dpdk.org/api/people/2383/?format=api", "name": "Sean Zhang", "email": "xiazhang@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/cover/20220211014530.77711-1-xiazhang@nvidia.com/mbox/", "series": [ { "id": 21617, "url": "http://patches.dpdk.org/api/series/21617/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21617", "date": "2022-02-11T01:45:26", "name": "Add support for GRE optional fields matching", "version": 2, "mbox": "http://patches.dpdk.org/series/21617/mbox/" } ], "comments": "http://patches.dpdk.org/api/covers/107311/comments/", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E872AA00BE;\n\tFri, 11 Feb 2022 02:45:53 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 728DD410E5;\n\tFri, 11 Feb 2022 02:45:53 +0100 (CET)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2044.outbound.protection.outlook.com [40.107.223.44])\n by mails.dpdk.org (Postfix) with ESMTP id 714C840683\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Sean Zhang <xiazhang@nvidia.com>", "To": "<thomas@monjalon.net>, <ferruh.yigit@intel.com>", "CC": "<dev@dpdk.org>", "Subject": "[v2 0/4] Add support for GRE optional fields matching", "Date": "Fri, 11 Feb 2022 03:45:26 +0200", "Message-ID": "<20220211014530.77711-1-xiazhang@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20220126084404.40178-1-xiazhang@nvidia.com>", "References": "<20220126084404.40178-1-xiazhang@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "faf1c012-b6e0-41eb-1f97-08d9ed003b4c", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB3818:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB381831E9E0D5C0E91FB5E373A2309@DM6PR12MB3818.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:9508;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n ARgfEzPcv/f/NZSRAqKxY+sJi5TwhZpycRcGWznjcDdNirI3KNFUZEiVf9N1Xxq3/OvElKtt+N+2i5ls/+sYvlqauJkXJLTEIJBftECB9cZTC4K7onO+KUthzwEzs1woyGpzX3pXlAhNVGHTmmtjn84r/EkzJ6DJRDhwcphQJuY8D1KDirXaWR8Vvveg9kxoLGh8SU87jPtIU4FMNBiuFRIOLvfuqtjL8ONKTylhEBkx1L+ZB3TME9LHgs0N3tkjooBSahlkLQg0Hl+AAWTuYkDnwYQNoHUBV5xjw6JUgCzUyFCv+k1KaT3G0lj78Dp1dUlySHtDte7t29UPhdX0lpTc2i2hohgiamgD5IzBaH1leWJz8m23dUuy5jp3FpFJGDNCpvOTcL5GQ0XukMw1llalh8nB38h1UIizKyn4YuzGnw/iNpEN56MiFpmX/Y5apile12J6ManJOwIWM7kkxAL0VLAR51ViM4Jz+Ki44z4KuvSz9pMFYXuZFJUDwHpmOjHnduVo3hTT+WXvMUD4UF4vVyORnKZS9THlXRPNi7Nxw9kfDjx9PvH18K5lPmpjL1Uzd+z3ua6hymr21b8DRVU9my7hyDPCHZAS9HgkEOTk+fZicQXDByPXEdjUsvfGfdUykjKuqv8o66YAdMadRxyNlON6wMhSn62w7TvOM5ylpI7KqLXXrRsfg1Z5mqJ34q6lmIO00UCbUFjU4NaNmw==", "X-Forefront-Antispam-Report": "CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(6286002)(82310400004)(2616005)(5660300002)(2906002)(186003)(8676002)(4326008)(8936002)(7696005)(70206006)(70586007)(16526019)(40460700003)(36860700001)(336012)(316002)(36756003)(426003)(55016003)(86362001)(110136005)(508600001)(1076003)(81166007)(356005)(26005)(47076005)(6666004)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "11 Feb 2022 01:45:49.9169 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n faf1c012-b6e0-41eb-1f97-08d9ed003b4c", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT057.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB3818", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch set adds support for matching optional fields of GRE header.\nThe optional fields are checksum, key and sequence number. Currently, key\nfield is supported with pattern gre_key item '.. / gre / gre_key value is\nxx / ..' with field gre_key in misc, but misc does not support matching of\nchecksum and sequence number of GRE.\nTo support matching of checksum and sequence number fields in GRE,\nrdma-core needs the capbility of misc5 and support tunnel_header 0-3. Since\ntunnel_header1 is used to match checksum, tunnel_header2 for key and\ntunnel_header3 for sequence by hardware. If checksum and sequence number\nnot present in the pattern, use misc as before for the matching.\nApplication can still use gre_key item 'gre_key value is xx' for key\nmatching, the effect is the same if use 'gre_option key is xx'.\nIf using gre_option item, the flags in gre item should be correspondingly\nset. For example, if using gre_option to match checksum, the c_bit should\nbe set '1' (.. / gre c_bit is 1 / gre_option checksum is xx / ..).\n\nchange in v2:\n-changed the struct defined in rte_flow for gre_option item.\n-fixed raw encap issue.\n\nSean Zhang (4):\n lib: add optional fields in GRE header\n ethdev: support GRE optional fields\n app/testpmd: add gre_option item command\n net/mlx5: support matching optional fields of GRE\n\n app/test-pmd/cmdline_flow.c | 72 +++++++++++++++\n doc/guides/nics/mlx5.rst | 8 ++\n doc/guides/prog_guide/rte_flow.rst | 17 ++++\n doc/guides/rel_notes/release_22_03.rst | 5 ++\n doc/guides/testpmd_app_ug/testpmd_funcs.rst | 6 ++\n drivers/common/mlx5/mlx5_devx_cmds.c | 3 +\n drivers/net/mlx5/linux/mlx5_os.c | 2 +\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_flow.c | 108 +++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow.h | 6 ++\n drivers/net/mlx5/mlx5_flow_dv.c | 130 ++++++++++++++++++++++++++++\n lib/ethdev/rte_flow.c | 1 +\n lib/ethdev/rte_flow.h | 19 ++++\n lib/net/rte_gre.h | 22 +++++\n 14 files changed, 400 insertions(+)" }