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{ "id": 101950, "url": "http://patches.dpdk.org/api/covers/101950/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/cover/20211018100141.3290956-1-dkozlyuk@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211018100141.3290956-1-dkozlyuk@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211018100141.3290956-1-dkozlyuk@nvidia.com", "date": "2021-10-18T10:01:37", "name": "[v7,0/4] net/mlx5: implicit mempool registration", "submitter": { "id": 2367, "url": "http://patches.dpdk.org/api/people/2367/?format=api", "name": "Dmitry Kozlyuk", "email": "dkozlyuk@oss.nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/cover/20211018100141.3290956-1-dkozlyuk@nvidia.com/mbox/", "series": [ { "id": 19728, "url": "http://patches.dpdk.org/api/series/19728/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19728", "date": "2021-10-18T10:01:37", "name": "net/mlx5: implicit mempool registration", "version": 7, "mbox": "http://patches.dpdk.org/series/19728/mbox/" } ], "comments": "http://patches.dpdk.org/api/covers/101950/comments/", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1F629A0C43;\n\tMon, 18 Oct 2021 12:02:09 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7EEF540141;\n\tMon, 18 Oct 2021 12:02:08 +0200 (CEST)", "from AZHDRRW-EX01.nvidia.com (azhdrrw-ex01.nvidia.com\n [20.51.104.162]) by mails.dpdk.org (Postfix) with ESMTP id 6E3194003C\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Dmitry Kozlyuk <dkozlyuk@oss.nvidia.com>", "To": "<dev@dpdk.org>", "Date": "Mon, 18 Oct 2021 13:01:37 +0300", "Message-ID": "<20211018100141.3290956-1-dkozlyuk@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211016200046.3176642-1-dkozlyuk@nvidia.com>", "References": "<20211016200046.3176642-1-dkozlyuk@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "22a29c9f-02a7-4e5f-d1a6-08d9921e5668", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB5566:", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB556683D31B7FE67E02CB5E54B9BC9@DM6PR12MB5566.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:10000;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n M2ubh+OPoEwbDdKjSpu8n923z7o8FFftdohX0hp7dXSryfq0fVRJ1QSlCGMAw7O7HvLPKeGnrXy9vTkZidewOzXm+VxJlYG2hwwB5zm6Mx9xzAooPaKL7hiv7kqO/7pl/o6KFFeXjAA+cSLKm6LSxPVYwWiz72kmbhJc6b+rBKfdFWUJqPPfKMSyeG+ynP9s50Xe5xxZuQ5bkM5J/RnxS5/hYKv2bB0h8sJ+Fz15MUt8jotsCMAwQ7kSUD5nVFaOx6y59VKq7hm/mCQF1jb1rjZa/48xJbBvSS3/8zdGNAjaH5pR9S5FtoXAlbc3APzoElkE6jje0voN3ibAvboFNEmQ/8C+0eET5PEcR1Ak+WFnM4Rc9qMqpd9KaYj1egLiJO3LjFMA58/zzAx2Hbj+9jlMuEK2HQLrYpMwdXElh2SfOlnN+iADnSDVVbq8oPWbx1HE5vZPnqvu3fG/pprLJBThkLSI/wRntgaPWvOBQKQ4OQHtX01BAk1RwNUZgBHeDlhHLWq7iBJBtu4FXoCDTmgOPdiPiIN8fHdjd38aMRL4SIEXYsP3Y0pAC4IDkf9JRFjGtalu4Dn0aZaGREwn1dslVhcneGiatn9fGGHVEVk0W3QYhytLRn+s8elDmUSdud2qVuNmqjcxWdyWl+3JQnWK4Euy/ISRUAZvGLYoQpXfJLelx3ZgPirEGgyqCxcu28xOGKSsrm63x+ZXQJ2BE4OKHqaATvGk3fqtvsP4fAPdffZnrLt+qjACYKA8BIrr86Q6Gk5TobAOArbzNt+ecoPfyMAq15fIgWs09Vea4p0=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(26005)(6666004)(7696005)(426003)(1076003)(47076005)(36756003)(6916009)(7636003)(86362001)(6286002)(356005)(336012)(8936002)(316002)(82310400003)(45080400002)(83380400001)(508600001)(36860700001)(2616005)(2906002)(966005)(16526019)(36906005)(8676002)(5660300002)(70206006)(70586007)(55016002)(186003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Oct 2021 10:02:04.3061 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 22a29c9f-02a7-4e5f-d1a6-08d9921e5668", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT043.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB5566", "Subject": "[dpdk-dev] [PATCH v7 0/4] net/mlx5: implicit mempool registration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "MLX5 hardware has its internal IOMMU where PMD registers the memory.\nOn the data path, PMD translates VA into a key consumed by the device\nIOMMU. It is impractical for the PMD to register all allocated memory\nbecause of increased lookup cost both in HW and SW. Most often mbuf\nmemory comes from mempools, so if PMD tracks them, it can almost always\nhave mbuf memory registered before an mbuf hits the PMD. This patchset\nadds such tracking in the PMD and internal API to support it.\n\nPlease see [1] for the discussion of the patch 2/4\nand how it can be useful outside of the MLX5 PMD.\n\n[1]: http://inbox.dpdk.org/dev/CH0PR12MB509112FADB778AB28AF3771DB9F99@CH0PR12MB5091.namprd12.prod.outlook.com/\n\nv7 (internal CI):\n 1. Fix unit test compilation issues with GCC.\n 2. Keep rte_mempool_event description non-internal: Doxygen treats\n it as not documented otherwise, \"doc\" target fails.\nv6:\n Fix compilation issue in proc-info (CI).\nv5:\n 1. Change non-IO flag inference + various fixes (Andrew).\n 2. Fix callback unregistration from secondary processes (Olivier).\n 3. Support non-IO flag in proc-dump (David).\n 4. Fix the usage of locks (Olivier).\n 5. Avoid resource leaks in unit test (Olivier).\nv4: (Andrew)\n 1. Improve mempool event callbacks unit tests and documentation.\n 2. Make MEMPOOL_F_NON_IO internal and automatically inferred.\n Add unit tests for the inference logic.\nv3: Improve wording and naming; fix typos (Thomas).\nv2 (internal review and testing):\n 1. Change tracked mempool event from being created (CREATE) to being\n fully populated (READY), which is the state PMD is interested in.\n 2. Unit test the new mempool callback API.\n 3. Remove bogus \"error\" messages in normal conditions.\n 4. Fixes in PMD.\n\nDmitry Kozlyuk (4):\n mempool: add event callbacks\n mempool: add non-IO flag\n common/mlx5: add mempool registration facilities\n net/mlx5: support mempool registration\n\n app/proc-info/main.c | 6 +-\n app/test/test_mempool.c | 360 +++++++++++++++\n doc/guides/nics/mlx5.rst | 13 +\n doc/guides/rel_notes/release_21_11.rst | 9 +\n drivers/common/mlx5/mlx5_common_mp.c | 50 +++\n drivers/common/mlx5/mlx5_common_mp.h | 14 +\n drivers/common/mlx5/mlx5_common_mr.c | 580 +++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_common_mr.h | 17 +\n drivers/common/mlx5/version.map | 5 +\n drivers/net/mlx5/linux/mlx5_mp_os.c | 44 ++\n drivers/net/mlx5/linux/mlx5_os.c | 4 +-\n drivers/net/mlx5/mlx5.c | 152 +++++++\n drivers/net/mlx5/mlx5.h | 10 +\n drivers/net/mlx5/mlx5_mr.c | 120 ++---\n drivers/net/mlx5/mlx5_mr.h | 2 -\n drivers/net/mlx5/mlx5_rx.h | 21 +-\n drivers/net/mlx5/mlx5_rxq.c | 13 +\n drivers/net/mlx5/mlx5_trigger.c | 77 +++-\n drivers/net/mlx5/windows/mlx5_os.c | 1 +\n lib/mempool/rte_mempool.c | 134 ++++++\n lib/mempool/rte_mempool.h | 64 +++\n lib/mempool/version.map | 8 +\n 22 files changed, 1586 insertions(+), 118 deletions(-)" }