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{ "id": 100169, "url": "http://patches.dpdk.org/api/covers/100169/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/cover/20210930172822.1949969-1-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210930172822.1949969-1-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210930172822.1949969-1-michaelba@nvidia.com", "date": "2021-09-30T17:28:04", "name": "[00/18] mlx5: sharing global MR cache between drivers", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/cover/20210930172822.1949969-1-michaelba@nvidia.com/mbox/", "series": [ { "id": 19311, "url": "http://patches.dpdk.org/api/series/19311/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=19311", "date": "2021-09-30T17:28:04", "name": "mlx5: sharing global MR cache between drivers", "version": 1, "mbox": "http://patches.dpdk.org/series/19311/mbox/" } ], "comments": "http://patches.dpdk.org/api/covers/100169/comments/", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 96201A0C43;\n\tThu, 30 Sep 2021 19:39:46 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1862640DDA;\n\tThu, 30 Sep 2021 19:39:46 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2057.outbound.protection.outlook.com [40.107.236.57])\n by mails.dpdk.org (Postfix) with ESMTP id 0F1AA4067E\n for <dev@dpdk.org>; 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dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "<michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Thomas Monjalon <thomas@monjalon.net>,\n Michael Baum <michaelba@oss.nvidia.com>", "Date": "Thu, 30 Sep 2021 20:28:04 +0300", "Message-ID": "<20210930172822.1949969-1-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "aeecd296-fabc-4f3d-ccc0-08d98437c12b", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB2793:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB279365E2BDA4614DA5A76576CCAA9@DM6PR12MB2793.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:4125;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n vhjFsNLgTj1q8i/g6zIOE7pzLTmzZxcsvcLRQv6CR6vCnGf1DGdBerCnnsNbc4qWeq7JknXvyWPz2DodxPDTxZ6RXv9DGROC1z3HTBIahWt3QMrREqrQd/n54FYX0Glmxs9SAzrQ/5n7yQPPHC6ZhOr8CeG4idU71NBJKy/yVY5qlYN2DrVbCGEm3wjvMKE3HNeGZxpM1a20P9Oy+uIaYAK5bqDTVAso7Sr+fSeglf/LANAuuBwoz3vNHwfTdrZRfrsoj6EawBZuthaNKLn0hi1awrjt/aBBP48FeGnmp0kbnws6ISLkpcEh0SgVoUoB1MLb7u1soIu9gROy3y+BnYn/lQMfv1rStljS/rplbEv4JT5ipKDHI25v7JBdLel/XefsIDwZerRvpeBa8n1NB24GIhTD0cRKN7YSgaXvqITS0tpB7gQ1eTM7T6ff5FH2BkCamyNqjWvEs4fIzavDp3JoIjInR5HkGnzFD6P9AtnK3qv9Md0s4PwhccPqUjLB6SqCUj2GyukBA8IuCMY+lWo5NWUBVQOJayih59nIz+sMN3MqwDuOkyNUHIlY7iByYSMOi5gArTkqvvOQp9LP2iAnmPbtBq5cK+JekPJnAZ8jOzmlYqSnL3ieIBRxBvzpZSK0pImmDpjZC4ZX0PIBJJgtnoQukJNAXRAx5cOmyECqSOKHq97tKGhjkzD26mKPRTIxAeLuYxIoxaaBGsGyB+RvP32xQPJx5IEplcET3m9io3qR4nEIuIt4z2c1uB+4//2oA5/Tx0Y/HbSv5OFtwgjw2MaWyNJ5YWb0apnkZxsk/3140m+InhpZPx3lZzsjdNHuJElNTwZZjs74nbuGFg==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(70206006)(54906003)(8936002)(966005)(1076003)(356005)(5660300002)(16526019)(186003)(7696005)(55016002)(2876002)(86362001)(316002)(7636003)(36756003)(2906002)(70586007)(107886003)(4326008)(26005)(6286002)(508600001)(83380400001)(6916009)(8676002)(36860700001)(82310400003)(336012)(2616005)(6666004)(47076005)(426003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Sep 2021 17:28:44.5918 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n aeecd296-fabc-4f3d-ccc0-08d98437c12b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT058.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB2793", "X-Mailman-Approved-At": "Thu, 30 Sep 2021 19:39:43 +0200", "Subject": "[dpdk-dev] [PATCH 00/18] mlx5: sharing global MR cache between\n drivers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Michael Baum <michaelba@oss.nvidia.com>\n\nThe MLNX PMD supports 5 classes (net, RegEx, vDPA, Compress and Crypto).\nThe various drivers are registered under the common driver, and managed\nby it.\nIn the common driver probing, it calls in a loop the probe function of\neach driver registered to it. Each driver creates for itself all the\nobjects required for communication with the hardware, as well as a\nglobal MR cache that manages memory mappings.\nThe management of the caches separately by the different drivers, is not\nvery efficient. In fact the same memory is managed several times and\neach caching handle is done by doubling the number of drivers, so we\nwant to manage this cache jointly by the common driver.\nThis feature will move management to common driver in two phases.\n\nPhase 1: sharing HW objects between drivers (11 patches)\nThe communication with the hardware - for any MR handle - is conducted\nby the Protection Domain, so we are motivated to share it between the\ndrivers. However, to create it we need to give the context of the\ndevice, so the context must also be shared between the drivers.\nAt this point we will share between the drivers the next trio (CTX, PD,\npdn) to create an infrastructure that will allow sharing of dependent\nobjects, and in particular the global MR cache.\nThe common driver itself will create this trio individually for all\ndrivers, before calling their probe function. As a parameter to the\nprobe function, it will give them a pointer to the structure containing\nthe trio.\n\nPhase 2: sharing global MR cache between drivers (7 patches)\nThe common driver will add to the structure containing the trio also the\nstructure that manages the global MR cache, and will keep a list of such\nstructures for memory management. In each driver, each queue will manage\nits own local MR cache. If the queue does not find its cache, it will\nswitch to searching the global MR cache shared by all. Caching access\nwill be through the pointer that the driver received as a parameter in\nprobing.\n\nDepends-on: series-19267 (\"mempool: add event callbacks\")\nhttps://patchwork.dpdk.org/project/dpdk/list/?series=19267\n\nDepends-on: series-19097 (\"net/mlx5: support new global device syntax\")\nhttps://patchwork.dpdk.org/project/dpdk/list/?series=19097\n\nMichael Baum (18):\n net/mlx5/windows: fix miss callback register for mem event\n common/mlx5: share basic probing with the internal drivers\n common/mlx5: share common definitions\n common/mlx5: share memory related devargs\n net/mlx5/windows: rearrange probing code\n common/mlx5: move basic probing functions to common\n net/mlx5: remove redundant flag in device config\n common/mlx5: share device context object\n common/mlx5: add ROCE disable in context device creation\n common/mlx5: share the protection domain object\n common/mlx5: share the HCA capabilities handle\n net/mlx5: remove redundancy in MR file\n common/mlx5: add MR ctrl init function\n common/mlx5: add global MR cache create function\n common/mlx5: share MR top-half search function\n common/mlx5: share MR management\n common/mlx5: support device DMA map and unmap\n common/mlx5: share MR mempool registration\n\n drivers/common/mlx5/linux/mlx5_common_os.c | 280 +++++++-\n drivers/common/mlx5/linux/mlx5_common_os.h | 16 +-\n drivers/common/mlx5/linux/mlx5_common_verbs.c | 96 ++-\n drivers/common/mlx5/linux/mlx5_nl.c | 2 +-\n drivers/common/mlx5/linux/mlx5_nl.h | 6 +-\n drivers/common/mlx5/mlx5_common.c | 596 +++++++++++++++---\n drivers/common/mlx5/mlx5_common.h | 96 +--\n drivers/common/mlx5/mlx5_common_defs.h | 45 ++\n drivers/common/mlx5/mlx5_common_mp.h | 11 +\n drivers/common/mlx5/mlx5_common_mr.c | 192 +++++-\n drivers/common/mlx5/mlx5_common_mr.h | 76 ++-\n drivers/common/mlx5/mlx5_common_private.h | 6 -\n drivers/common/mlx5/mlx5_devx_cmds.h | 12 +-\n drivers/common/mlx5/mlx5_malloc.h | 1 -\n drivers/common/mlx5/version.map | 29 +-\n drivers/common/mlx5/windows/mlx5_common_os.c | 245 ++++++-\n drivers/common/mlx5/windows/mlx5_common_os.h | 9 +-\n drivers/compress/mlx5/mlx5_compress.c | 223 ++-----\n drivers/crypto/mlx5/mlx5_crypto.c | 201 +-----\n drivers/crypto/mlx5/mlx5_crypto.h | 6 +-\n drivers/crypto/mlx5/mlx5_crypto_dek.c | 5 +-\n drivers/net/mlx5/linux/mlx5_ethdev_os.c | 6 +-\n drivers/net/mlx5/linux/mlx5_mp_os.c | 12 +-\n drivers/net/mlx5/linux/mlx5_os.c | 511 ++++-----------\n drivers/net/mlx5/linux/mlx5_verbs.c | 99 +--\n drivers/net/mlx5/linux/mlx5_verbs.h | 2 -\n drivers/net/mlx5/meson.build | 1 -\n drivers/net/mlx5/mlx5.c | 241 ++-----\n drivers/net/mlx5/mlx5.h | 57 +-\n drivers/net/mlx5/mlx5_defs.h | 22 +-\n drivers/net/mlx5/mlx5_devx.c | 39 +-\n drivers/net/mlx5/mlx5_flow.c | 6 +-\n drivers/net/mlx5/mlx5_flow_aso.c | 50 +-\n drivers/net/mlx5/mlx5_flow_dv.c | 66 +-\n drivers/net/mlx5/mlx5_flow_verbs.c | 4 +-\n drivers/net/mlx5/mlx5_mr.c | 397 ------------\n drivers/net/mlx5/mlx5_mr.h | 26 -\n drivers/net/mlx5/mlx5_rx.c | 16 +-\n drivers/net/mlx5/mlx5_rx.h | 20 +-\n drivers/net/mlx5/mlx5_rxq.c | 11 +-\n drivers/net/mlx5/mlx5_rxtx.c | 1 -\n drivers/net/mlx5/mlx5_rxtx.h | 27 -\n drivers/net/mlx5/mlx5_rxtx_vec.h | 1 -\n drivers/net/mlx5/mlx5_trigger.c | 8 +-\n drivers/net/mlx5/mlx5_tx.c | 1 -\n drivers/net/mlx5/mlx5_tx.h | 30 +-\n drivers/net/mlx5/mlx5_txpp.c | 23 +-\n drivers/net/mlx5/mlx5_txq.c | 10 +-\n drivers/net/mlx5/windows/mlx5_ethdev_os.c | 12 +-\n drivers/net/mlx5/windows/mlx5_os.c | 402 ++----------\n drivers/regex/mlx5/mlx5_regex.c | 138 +---\n drivers/regex/mlx5/mlx5_regex.h | 27 +-\n drivers/regex/mlx5/mlx5_regex_control.c | 19 +-\n drivers/regex/mlx5/mlx5_regex_fastpath.c | 47 +-\n drivers/regex/mlx5/mlx5_rxp.c | 62 +-\n drivers/vdpa/mlx5/mlx5_vdpa.c | 212 +------\n drivers/vdpa/mlx5/mlx5_vdpa.h | 5 +-\n drivers/vdpa/mlx5/mlx5_vdpa_event.c | 25 +-\n drivers/vdpa/mlx5/mlx5_vdpa_lm.c | 6 +-\n drivers/vdpa/mlx5/mlx5_vdpa_mem.c | 13 +-\n drivers/vdpa/mlx5/mlx5_vdpa_steer.c | 11 +-\n drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 15 +-\n 62 files changed, 2065 insertions(+), 2769 deletions(-)\n create mode 100644 drivers/common/mlx5/mlx5_common_defs.h\n delete mode 100644 drivers/net/mlx5/mlx5_mr.c\n delete mode 100644 drivers/net/mlx5/mlx5_mr.h" }